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xilinx: Add simulation models for MULT18X18* and DSP48A*.

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This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
This commit is contained in:
Marcin Kościelnicki 2019-11-18 03:47:56 +01:00 • committed by Marcin Kościelnicki
parent 9ee3c57e46
commit 7a9081440c
3 changed files with 516 additions and 132 deletions
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127
techlibs/xilinx/cells_xtra.v
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@ -6218,133 +6218,6 @@ module URAM288_BASE (...);
input SLEEP;
endmodule
module MULT18X18 (...);
output [35:0] P;
input [17:0] A;
input [17:0] B;
endmodule
module MULT18X18S (...);
output [35:0] P;
input [17:0] A;
input [17:0] B;
(* clkbuf_sink *)
input C;
input CE;
input R;
endmodule
module MULT18X18SIO (...);
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer PREG = 1;
output [17:0] BCOUT;
output [35:0] P;
input [17:0] A;
input [17:0] B;
input [17:0] BCIN;
input CEA;
input CEB;
input CEP;
(* clkbuf_sink *)
input CLK;
input RSTA;
input RSTB;
input RSTP;
endmodule
module DSP48A (...);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
parameter integer B1REG = 1;
parameter integer CARRYINREG = 1;
parameter CARRYINSEL = "CARRYIN";
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter RSTTYPE = "SYNC";
output [17:0] BCOUT;
output CARRYOUT;
output [47:0] P;
output [47:0] PCOUT;
input [17:0] A;
input [17:0] B;
input [47:0] C;
input CARRYIN;
input CEA;
input CEB;
input CEC;
input CECARRYIN;
input CED;
input CEM;
input CEOPMODE;
input CEP;
(* clkbuf_sink *)
input CLK;
input [17:0] D;
input [7:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTB;
input RSTC;
input RSTCARRYIN;
input RSTD;
input RSTM;
input RSTOPMODE;
input RSTP;
endmodule
module DSP48A1 (...);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
parameter integer B1REG = 1;
parameter integer CARRYINREG = 1;
parameter integer CARRYOUTREG = 1;
parameter CARRYINSEL = "OPMODE5";
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter RSTTYPE = "SYNC";
output [17:0] BCOUT;
output CARRYOUT;
output CARRYOUTF;
output [35:0] M;
output [47:0] P;
output [47:0] PCOUT;
input [17:0] A;
input [17:0] B;
input [47:0] C;
input CARRYIN;
input CEA;
input CEB;
input CEC;
input CECARRYIN;
input CED;
input CEM;
input CEOPMODE;
input CEP;
(* clkbuf_sink *)
input CLK;
input [17:0] D;
input [7:0] OPMODE;
input [47:0] PCIN;
input RSTA;
input RSTB;
input RSTC;
input RSTCARRYIN;
input RSTD;
input RSTM;
input RSTOPMODE;
input RSTP;
endmodule
module DSP48 (...);
parameter integer AREG = 1;
parameter integer BREG = 1;