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xilinx: Add simulation models for MULT18X18* and DSP48A*.

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This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
This commit is contained in:
Marcin Kościelnicki 2019-11-18 03:47:56 +01:00 • committed by Marcin Kościelnicki
parent 9ee3c57e46
commit 7a9081440c
3 changed files with 516 additions and 132 deletions
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10
techlibs/xilinx/cells_xtra.py
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@ -204,11 +204,11 @@ CELLS = [
Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
# Multipliers and DSP.
Cell('MULT18X18'), # Spartan 3
Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3
Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
# Cell('MULT18X18'), # Virtex 2, Spartan 3
# Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3
# Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E
# Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP
# Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6
Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4
Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5
#Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7