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Merge pull request #2024 from YosysHQ/eddie/primitive_src

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verilog: set src attribute for primitives
This commit is contained in:
Eddie Hung 2020-05-05 06:49:18 -07:00 • committed by GitHub
commit 7a62ee57b4
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3 changed files with 22 additions and 2 deletions
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4
frontends/ast/simplify.cc
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@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *node = children_list[1];
if (op_type != AST_POS)
for (size_t i = 2; i < children_list.size(); i++)
for (size_t i = 2; i < children_list.size(); i++) {
node = new AstNode(op_type, node, children_list[i]);
node->location = location;
}
if (invert_results)
node = new AstNode(AST_BIT_NOT, node);

4
frontends/verilog/verilog_parser.y
View file

@ -1749,7 +1749,9 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')';
} '(' cell_port_list ')' {
SET_AST_NODE_LOC(astbuf2, @1, @$);
}
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;

16
tests/various/primitives.ys Normal file
View file

@ -0,0 +1,16 @@
read_verilog <<EOT
module top(input a, b, output [5:0] y);
and (y[0], a, b);
nand (y[1], a, b);
or (y[2], a, b);
nor (y[3], a, b);
xor (y[4], a, b);
xnor (y[5], a, b);
endmodule
EOT
select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i