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Merge pull request #2024 from YosysHQ/eddie/primitive_src

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verilog: set src attribute for primitives
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Eddie Hung 2020-05-05 06:49:18 -07:00 • committed by GitHub
commit 7a62ee57b4
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3 changed files with 22 additions and 2 deletions
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frontends/verilog/verilog_parser.y
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@ -1749,7 +1749,9 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')';
} '(' cell_port_list ')' {
SET_AST_NODE_LOC(astbuf2, @1, @$);
}
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;