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	manual: explain $tribuf cell.
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			@ -119,6 +119,12 @@ than one bit from \B{S} is set the output is undefined. Cells of this type are u
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``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by
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an optimization).
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The {\tt \$tribuf} cell is used to implement tristate logic. Cells of this type have a \B{WIDTH}
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parameter and inputs \B{A} and \B{EN} and an output \B{Y}. The \B{A} input and \B{Y} output are
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\B{WIDTH} bits wide, and the \B{EN} input is one bit wide. When \B{EN} is 0, the output \B{Y}
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is not driven. When \B{EN} is 1, the value from \B{A} input is sent to the \B{Y} output. Therefore,
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the {\tt \$tribuf} cell implements the function \lstinline[language=Verilog]; Y = EN ? A : 'bz;.
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Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements
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usually results in trees of multiplexer cells. Many passes (from various
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optimizations to FSM extraction) heavily depend on these multiplexer trees to
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			@ -476,6 +482,10 @@ Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dl
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Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
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\end{fixme}
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\begin{fixme}
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Add information about {\tt \$\_TBUF\_} cells.
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\end{fixme}
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\begin{fixme}
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Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_ORNOT\_},
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{\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
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