diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 13f6acec4..73ffcbf3e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -95,7 +95,8 @@ bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) {
 
 PRIVATE_NAMESPACE_BEGIN
 
-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase;
+bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs,
+  noparallelcase, default_params;
 int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter;
 dict<RTLIL::IdString, int> auto_name_map;
 std::set<RTLIL::IdString> reg_wires;
@@ -2445,8 +2446,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		f << indent + "  " << "reg " << id(initial_id) << " = 0;\n";
 	}
 
-	for (auto p : module->parameter_default_values)
-		dump_parameter(f, indent + "  ", p.first, p.second);
+	if (default_params)
+		for (auto p : module->parameter_default_values)
+			dump_parameter(f, indent + "  ", p.first, p.second);
 
 	// first dump input / output according to their order in module->ports
 	for (auto port : module->ports)
@@ -2555,6 +2557,10 @@ struct VerilogBackend : public Backend {
 		log("        use 'defparam' statements instead of the Verilog-2001 syntax for\n");
 		log("        cell parameters.\n");
 		log("\n");
+		log("    -default_params\n");
+		log("        emit module parameter declarations from\n");
+		log("        parameter_default_values.\n");
+		log("\n");
 		log("    -blackboxes\n");
 		log("        usually modules with the 'blackbox' attribute are ignored. with\n");
 		log("        this option set only the modules with the 'blackbox' attribute\n");
@@ -2592,6 +2598,7 @@ struct VerilogBackend : public Backend {
 		siminit = false;
 		simple_lhs = false;
 		noparallelcase = false;
+		default_params = false;
 		auto_prefix = "";
 
 		bool blackboxes = false;
@@ -2652,6 +2659,10 @@ struct VerilogBackend : public Backend {
 				defparam = true;
 				continue;
 			}
+			if (arg == "-defaultparams") {
+				default_params = true;
+				continue;
+			}
 			if (arg == "-decimal") {
 				decimal = true;
 				continue;
diff --git a/tests/various/json_param_defaults.ys b/tests/various/json_param_defaults.ys
index 2624ab884..45e312de2 100644
--- a/tests/various/json_param_defaults.ys
+++ b/tests/various/json_param_defaults.ys
@@ -3,6 +3,6 @@ read_verilog -sv json_param_defaults.v
 write_json temp/json_param_defaults.json
 design -reset
 read_json temp/json_param_defaults.json
-write_verilog -noattr temp/json_param_defaults.v
+write_verilog -noattr -defaultparams temp/json_param_defaults.v
 ! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v
 ! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v