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Progress in presentation

This commit is contained in:
Clifford Wolf 2014-02-21 14:59:59 +01:00
parent 038eac7414
commit 79edcd4318
6 changed files with 113 additions and 32 deletions

View file

@ -1,4 +1,3 @@
(* techmap_celltype = "$mul" *)
module mul_swap_ports (A, B, Y);
@ -12,7 +11,7 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
\$mul #(
.A_SIGNED(B_SIGNED),
@ -27,4 +26,3 @@ wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
);
endmodule

View file

@ -38,6 +38,6 @@ techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1e -format pdf -notitle test1
show -prefix macc_xilinx_test2e -format pdf -notitle test2
design -load
design -load __macc_xilinx_xmap
show -prefix macc_xilinx_xmap -format pdf -notitle

View file

@ -1,4 +1,3 @@
module \$__mul_wrapper (A, B, Y);
parameter A_SIGNED = 0;
@ -7,8 +6,8 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [24:0] A;
input [17:0] B;
input [17:0] A;
input [24:0] B;
output [47:0] Y;
wire [A_WIDTH-1:0] A_ORIG = A;
@ -60,4 +59,3 @@ assign Y = Y_ORIG;
);
endmodule

View file

@ -1,4 +1,3 @@
(* techmap_celltype = "$mul" *)
module mul_wrap (A, B, Y);
@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire [24:0] A_25 = A;
wire [17:0] B_18 = B;
wire [17:0] A_18 = A;
wire [24:0] B_25 = B;
wire [47:0] Y_48;
assign Y = Y_48;
@ -26,7 +25,7 @@ initial begin
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH < 4 || B_WIDTH < 4)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH > 25 || B_WIDTH > 18)
if (A_WIDTH > 18 || B_WIDTH > 25)
_TECHMAP_FAIL_ <= 1;
if (A_WIDTH*B_WIDTH < 100)
_TECHMAP_FAIL_ <= 1;
@ -39,8 +38,8 @@ end
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A_25),
.B(B_18),
.A(A_18),
.B(B_25),
.Y(Y_48)
);
@ -88,4 +87,3 @@ end
);
endmodule

View file

@ -1,7 +1,7 @@
module DSP48_MACC (a, b, c, y);
input [24:0] a;
input [17:0] b;
input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;