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Progress in presentation
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038eac7414
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6 changed files with 113 additions and 32 deletions
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@ -1,4 +1,3 @@
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(* techmap_celltype = "$mul" *)
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module mul_swap_ports (A, B, Y);
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@ -12,7 +11,7 @@ input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
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wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
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\$mul #(
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.A_SIGNED(B_SIGNED),
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@ -27,4 +26,3 @@ wire _TECHMAP_FAIL_ = A_WIDTH >= B_WIDTH;
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);
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endmodule
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@ -38,6 +38,6 @@ techmap -map macc_xilinx_unwrap_map.v;;
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show -prefix macc_xilinx_test1e -format pdf -notitle test1
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show -prefix macc_xilinx_test2e -format pdf -notitle test2
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design -load
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design -load __macc_xilinx_xmap
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show -prefix macc_xilinx_xmap -format pdf -notitle
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@ -1,4 +1,3 @@
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module \$__mul_wrapper (A, B, Y);
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parameter A_SIGNED = 0;
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@ -7,8 +6,8 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [24:0] A;
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input [17:0] B;
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input [17:0] A;
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input [24:0] B;
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output [47:0] Y;
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wire [A_WIDTH-1:0] A_ORIG = A;
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@ -60,4 +59,3 @@ assign Y = Y_ORIG;
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);
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endmodule
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@ -1,4 +1,3 @@
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(* techmap_celltype = "$mul" *)
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module mul_wrap (A, B, Y);
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@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [24:0] A_25 = A;
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wire [17:0] B_18 = B;
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wire [17:0] A_18 = A;
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wire [24:0] B_25 = B;
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wire [47:0] Y_48;
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assign Y = Y_48;
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@ -26,7 +25,7 @@ initial begin
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH < 4 || B_WIDTH < 4)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH > 25 || B_WIDTH > 18)
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if (A_WIDTH > 18 || B_WIDTH > 25)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH*B_WIDTH < 100)
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_TECHMAP_FAIL_ <= 1;
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@ -39,8 +38,8 @@ end
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_25),
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.B(B_18),
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.A(A_18),
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.B(B_25),
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.Y(Y_48)
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);
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@ -88,4 +87,3 @@ end
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);
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endmodule
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@ -1,7 +1,7 @@
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module DSP48_MACC (a, b, c, y);
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input [24:0] a;
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input [17:0] b;
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input [17:0] a;
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input [24:0] b;
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input [47:0] c;
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output [47:0] y;
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