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verilog: Bufnorm cell backend and frontend support

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This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
This commit is contained in:
Jannis Harder 2025-09-16 15:49:36 +02:00
parent 4f239b536b
commit 79e05a195d
3 changed files with 69 additions and 9 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -493,7 +493,7 @@ TIME_SCALE_SUFFIX [munpf]?s
\"{3}(\"{0,2}([^\\"]|\\.|\\\n))*\"{3} { return process_str(yytext + 3, yyleng - 6, true, out_loc); }
and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1|tran {
auto val = std::make_unique<std::string>(YYText());
return parser::make_TOK_PRIMITIVE(std::move(val), out_loc);
}