From 79d1e265a53292d4fcec4e7f64819ad5fd045fb0 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Tue, 14 Jul 2026 10:39:29 +0200
Subject: [PATCH] Test.

---
 tests/proc/proc_latches.ys | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tests/proc/proc_latches.ys b/tests/proc/proc_latches.ys
index 91749b6a7..ba22bf879 100644
--- a/tests/proc/proc_latches.ys
+++ b/tests/proc/proc_latches.ys
@@ -22,6 +22,20 @@ logger -check-expected
 
 design -reset
 
+# always_latch is exempt
+read_verilog -sv <<EOT
+module top(input g, d, output reg q);
+always_latch if (g) q <= d;
+endmodule
+EOT
+logger -expect-no-warnings
+logger -expect log "Latch inferred for signal .* from always_latch process" 1
+proc -latches error
+logger -check-expected
+select -assert-count 1 t:$dlatch a:always_latch %i
+
+design -reset
+
 # error
 read_verilog <<EOT
 module top(input g, rn, d, output reg q);