mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 03:10:26 +00:00
Code Activity

Corrected spelling mistakes found by lintian

Browse source
This commit is contained in:
Ruben Undheim 2014-09-06 08:47:06 +02:00
parent 01ef34c147
commit 79cbf9067c
22 changed files with 39 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_share.cc
View file

@ -720,7 +720,7 @@ struct MemorySharePass : public Pass {
log(" address, then this feedback path is converted to a write port with\n");
log(" byte/part enable signals.\n");
log("\n");
log(" - When multiple write ports access the same adress then this is converted\n");
log(" - When multiple write ports access the same address then this is converted\n");
log(" to a single write port with a more complex data and/or enable logic path.\n");
log("\n");
log(" - When multiple write ports are never accessed at the same time (a SAT\n");