mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 15:24:57 +00:00
Code Activity

Corrected spelling mistakes found by lintian

Browse source
This commit is contained in:
Ruben Undheim 2014-09-06 08:47:06 +02:00
parent 01ef34c147
commit 79cbf9067c
22 changed files with 39 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

2
manual/manual.tex
View file

@ -144,7 +144,7 @@ Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries or when
testing new synthesis algorithms it might be neccessary to write a custom HDL
testing new synthesis algorithms it might be necessary to write a custom HDL
synthesis tool or add new features to an existing one. It this cases the
availability of a Free and Open Source (FOSS) synthesis tool that can be used
as basis for custom tools would be helpful.