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Big rework; flop info now mostly in cells_sim.v

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This commit is contained in:
Eddie Hung 2019-09-28 23:48:17 -07:00
parent cfa6dd61ef
commit 79b6edb639
9 changed files with 500 additions and 456 deletions
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4
techlibs/xilinx/synth_xilinx.cc
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@ -276,9 +276,9 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("begin")) {
if (vpr)
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
run("read_verilog -lib +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
if (help_mode)
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");