mirror of
https://github.com/YosysHQ/yosys
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Big rework; flop info now mostly in cells_sim.v
This commit is contained in:
Eddie Hung
parent
cfa6dd61ef
commit
79b6edb639
9 changed files with 500 additions and 456 deletions
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@ -240,6 +240,7 @@ endmodule
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
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(* abc_box_id=1001, lib_whitebox, abc9_flop *)
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module FDRE (
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(* abc_arrival=303 *)
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output reg Q,
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@ -257,35 +258,72 @@ module FDRE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R == !IS_R_INVERTED) \$nextQ = 1'b0; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b0: always @(posedge C) Q <= \$nextQ ;
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1'b1: always @(negedge C) Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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module FDSE (
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(* abc_box_id=1002, lib_whitebox, abc9_flop *)
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module FDRE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_C_INVERTED" *)
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input C,
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input CE,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D,
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(* invertible_pin = "IS_S_INVERTED" *)
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input S
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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endcase endgenerate
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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always @(negedge C) Q <= \$nextQ ;
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`endif
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endmodule
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(* abc_box_id=1003, lib_whitebox, abc9_flop *)
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module FDCE (
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(* abc_arrival=303 *)
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output reg Q,
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@ -303,14 +341,78 @@ module FDCE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC_ASYNC box by abc_map.v
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
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2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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(* abc_box_id=1004, lib_whitebox, abc9_flop *)
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module FDCE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC_ASYNC box by abc_map.v
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
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`endif
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endmodule
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(* abc_box_id=1005, lib_whitebox, abc9_flop *)
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module FDPE (
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(* abc_arrival=303 *)
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output reg Q,
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@ -328,50 +430,40 @@ module FDPE (
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Since this is an async flop, async behaviour is also dealt with
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// using the $_ABC_ASYNC box by abc_map.v
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// Special signal indicating clock domain
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// (used to partition the module so that `abc9' only performs
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
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2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
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2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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module FDRE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, R
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
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endmodule
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module FDSE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
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endmodule
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module FDCE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, CLR
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);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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(* abc_box_id=1006, lib_whitebox, abc9_flop *)
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module FDPE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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@ -381,7 +473,115 @@ module FDPE_1 (
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (CE) Q <= D; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
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// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
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// In order to achieve clock-enable behaviour, the current value
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// of the sequential output is required which Yosys will
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// connect to the special `\$currQ' wire.
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// Since this is an async flop, async behaviour is also dealt with
|
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// using the $_ABC_ASYNC box by abc_map.v
|
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// Special signal indicating clock domain
|
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// (used to partition the module so that `abc9' only performs
|
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// sequential synthesis (reachability analysis) correctly on
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// one domain at a time)
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wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
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`endif
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endmodule
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(* abc_box_id=1007, lib_whitebox, abc9_flop *)
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module FDSE (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_C_INVERTED" *)
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input C,
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input CE,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D,
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(* invertible_pin = "IS_S_INVERTED" *)
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input S
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);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (S == !IS_S_INVERTED) \$nextQ = 1'b1; else if (CE) \$nextQ = D ^ IS_D_INVERTED; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `\$currQ' wire.
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
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// sequential synthesis (reachability analysis) correctly on
|
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// one domain at a time)
|
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wire [1:0] \$abc9_clock = {C, IS_C_INVERTED};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
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always @* Q = \$nextQ ;
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`else
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assign \$currQ = Q;
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generate case (|IS_C_INVERTED)
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1'b0: always @(posedge C) Q <= \$nextQ ;
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1'b1: always @(negedge C) Q <= \$nextQ ;
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endcase endgenerate
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`endif
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endmodule
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(* abc_box_id=1008, lib_whitebox, abc9_flop *)
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module FDSE_1 (
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(* abc_arrival=303 *)
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output reg Q,
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(* clkbuf_sink *)
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input C,
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input CE, D, S
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);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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wire \$currQ ;
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reg \$nextQ ;
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always @* if (S) \$nextQ = 1'b1; else if (CE) \$nextQ = D; else \$nextQ = \$currQ ;
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`ifdef _ABC
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// `abc9' requires that complex flops be split into a combinatorial
|
||||
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
|
||||
// In order to achieve clock-enable behaviour, the current value
|
||||
// of the sequential output is required which Yosys will
|
||||
// connect to the special `\$currQ' wire.
|
||||
|
||||
// Special signal indicating clock domain
|
||||
// (used to partition the module so that `abc9' only performs
|
||||
// sequential synthesis (reachability analysis) correctly on
|
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// one domain at a time)
|
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wire [1:0] \$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
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// Special signal indicating control domain
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// (which, combined with this spell type, encodes to `abc9'
|
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// which flops may be merged together)
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wire [3:0] \$abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
|
||||
always @* Q = \$nextQ ;
|
||||
`else
|
||||
assign \$currQ = Q;
|
||||
always @(negedge C) Q <= \$nextQ ;
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
|
|
|
|||
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Reference in a new issue