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Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed

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peeopt.shiftmul: Add a signedness check.
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clairexen 2020-08-20 16:23:07 +02:00 • committed by GitHub
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read_verilog <<EOT
module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
wire [5:0] t = x * 3;
assign o = a >> t;
endmodule
EOT
wreduce
equiv_opt -assert peepopt