mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

Fix merge issues

Browse source
This commit is contained in:
Eddie Hung 2019-10-04 17:21:14 -07:00
parent 7a45cd5856
commit 7959e9d6b2
6 changed files with 14 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/techmap/techmap.cc
View file

@ -256,14 +256,6 @@ struct TechmapWorker
if (w->attributes.count(ID(src)))
w->add_strpool_attribute(ID(src), extra_src_attrs);
}
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) {
IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
Wire *replace_w = module->addWire(replace_name, it.second);
module->connect(replace_w, w);
}
design->select(module, w);
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {