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More progress on Firrtl backend.

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Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
This commit is contained in:
Adam Izraelevitz 2016-11-21 17:28:17 -08:00
parent 69468d5a16
commit 794cec0016
3 changed files with 181 additions and 27 deletions
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19
backends/firrtl/test.sh
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@ -1,16 +1,20 @@
#!/bin/bash
set -ex
../../yosys -p 'prep -nordff; write_firrtl test.fir' test.v
cd ../../
make
cd backends/firrtl
firrtl -i test.fir -o test_out.v
../../yosys -q -p 'prep -nordff; write_firrtl test.fir' $1
../../yosys -p '
read_verilog test.v
rename test gold
firrtl -i test.fir -o test_out.v -ll Info
../../yosys -p "
read_verilog $1
rename Top gold
read_verilog test_out.v
rename test gate
rename Top gate
prep
memory_map
@ -18,5 +22,4 @@ firrtl -i test.fir -o test_out.v
hierarchy -top miter
sat -verify -prove trigger 0 -set-init-zero -seq 10 miter
'
"