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Merge pull request #1119 from YosysHQ/eddie/fix1118

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Make genvar a signed type
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Clifford Wolf 2019-06-21 10:13:13 +02:00 • committed by GitHub
commit 78e7a6f6f2
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2 changed files with 12 additions and 0 deletions
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1
frontends/verilog/verilog_parser.y
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@ -517,6 +517,7 @@ wire_type_token:
TOK_GENVAR { TOK_GENVAR {
astbuf3->type = AST_GENVAR; astbuf3->type = AST_GENVAR;
astbuf3->is_reg = true; astbuf3->is_reg = true;
astbuf3->is_signed = true;
astbuf3->range_left = 31; astbuf3->range_left = 31;
astbuf3->range_right = 0; astbuf3->range_right = 0;
} | } |

11
tests/simple/generate.v
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@ -148,3 +148,14 @@ generate
endgenerate endgenerate
assign out = steps[WIDTH].outer[0].val; assign out = steps[WIDTH].outer[0].val;
endmodule endmodule
// ------------------------------------------
module gen_test6(output [3:0] o);
generate
genvar i;
for (i = 3; i >= 0; i = i-1) begin
assign o[i] = 1'b0;
end
endgenerate
endmodule