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Merge pull request #1119 from YosysHQ/eddie/fix1118

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Make genvar a signed type
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Clifford Wolf 2019-06-21 10:13:13 +02:00 • committed by GitHub
commit 78e7a6f6f2
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frontends/verilog/verilog_parser.y
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@ -517,6 +517,7 @@ wire_type_token:
TOK_GENVAR {
astbuf3->type = AST_GENVAR;
astbuf3->is_reg = true;
astbuf3->is_signed = true;
astbuf3->range_left = 31;
astbuf3->range_right = 0;
} |