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https://github.com/YosysHQ/yosys
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Transform all "\\*" identifiers into ID()
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parent
9f98241010
commit
78ba8b8574
25 changed files with 782 additions and 782 deletions
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@ -62,12 +62,12 @@ struct ZinitPass : public Pass {
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for (auto wire : module->selected_wires())
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{
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if (wire->attributes.count("\\init") == 0)
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if (wire->attributes.count(ID(\\init)) == 0)
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continue;
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SigSpec wirebits = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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wire->attributes.erase("\\init");
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Const initval = wire->attributes.at(ID(\\init));
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wire->attributes.erase(ID(\\init));
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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@ -103,8 +103,8 @@ struct ZinitPass : public Pass {
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if (!dff_types.count(cell->type))
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continue;
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SigSpec sig_d = sigmap(cell->getPort("\\D"));
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SigSpec sig_q = sigmap(cell->getPort("\\Q"));
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SigSpec sig_d = sigmap(cell->getPort(ID(\\D)));
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SigSpec sig_q = sigmap(cell->getPort(ID(\\Q)));
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if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
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continue;
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@ -120,14 +120,14 @@ struct ZinitPass : public Pass {
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}
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Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
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initwire->attributes["\\init"] = initval;
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initwire->attributes[ID(\\init)] = initval;
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval.bits.at(i) == State::S1)
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{
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sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
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module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
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initwire->attributes["\\init"].bits.at(i) = State::S0;
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initwire->attributes[ID(\\init)].bits.at(i) = State::S0;
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}
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else
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{
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@ -137,8 +137,8 @@ struct ZinitPass : public Pass {
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log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
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log_signal(sig_q), log_signal(initval));
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cell->setPort("\\D", sig_d);
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cell->setPort("\\Q", initwire);
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cell->setPort(ID(\\D), sig_d);
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cell->setPort(ID(\\Q), initwire);
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}
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for (auto &it : initbits)
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