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Transform all "\\*" identifiers into ID()

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This commit is contained in:
Eddie Hung 2019-08-15 10:19:29 -07:00
parent 9f98241010
commit 78ba8b8574
25 changed files with 782 additions and 782 deletions
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14
passes/techmap/iopadmap.cc
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@ -180,7 +180,7 @@ struct IopadmapPass : public Pass {
for (auto cell : module->cells())
if (cell->type == ID($_TBUF_)) {
SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
SigBit bit = sigmap(cell->getPort(ID(\\Y)).as_bit());
tbuf_bits[bit].first = cell->name;
}
@ -212,8 +212,8 @@ struct IopadmapPass : public Pass {
if (tbuf_cell == nullptr)
continue;
SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
SigBit en_sig = tbuf_cell->getPort(ID(\\E)).as_bit();
SigBit data_sig = tbuf_cell->getPort(ID(\\A)).as_bit();
if (wire->port_input && !tinoutpad_celltype.empty())
{
@ -226,7 +226,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
cell->attributes["\\keep"] = RTLIL::Const(1);
cell->attributes[ID(\\keep)] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn);
@ -263,7 +263,7 @@ struct IopadmapPass : public Pass {
cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
cell->attributes["\\keep"] = RTLIL::Const(1);
cell->attributes[ID(\\keep)] = RTLIL::Const(1);
for (auto cn : tbuf_cache.second) {
auto c = module->cell(cn);
@ -390,7 +390,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
cell->attributes["\\keep"] = RTLIL::Const(1);
cell->attributes[ID(\\keep)] = RTLIL::Const(1);
}
}
else
@ -403,7 +403,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes["\\keep"] = RTLIL::Const(1);
cell->attributes[ID(\\keep)] = RTLIL::Const(1);
}
wire->port_id = 0;