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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl

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This commit is contained in:
Eddie Hung 2019-08-23 11:32:44 -07:00
commit 78b7d8f531
9 changed files with 43 additions and 20 deletions
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1
Brewfile
View file

@ -6,3 +6,4 @@ brew "git"
brew "graphviz"
brew "pkg-config"
brew "python3"
brew "tcl-tk"

2
Makefile
View file

@ -91,8 +91,10 @@ PLUGIN_LDFLAGS += -undefined dynamic_lookup
ifneq ($(shell which brew),)
BREW_PREFIX := $(shell brew --prefix)/opt
$(info $$BREW_PREFIX is [${BREW_PREFIX}])
ifeq ($(ENABLE_PYOSYS),1)
CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
LDFLAGS += -L$(BREW_PREFIX)/boost/lib
endif
CXXFLAGS += -I$(BREW_PREFIX)/readline/include
LDFLAGS += -L$(BREW_PREFIX)/readline/lib
PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)

7
README.md
View file

@ -69,11 +69,14 @@ prerequisites for building yosys:
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
Similarily, on Mac OS X Homebrew can be used to install dependencies:
$ brew tap Homebrew/bundle && brew bundle
or MacPorts:
$ sudo port install bison flex readline gawk libffi \
git graphviz pkgconfig python36 boost zlib
git graphviz pkgconfig python36 boost zlib tcl
On FreeBSD use the following command to install all prerequisites:

3
frontends/ast/simplify.cc
View file

@ -151,7 +151,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
reg->is_reg = true;
reg->is_signed = node->is_signed;
for (auto &it : node->attributes)
reg->attributes.emplace(it.first, it.second->clone());
if (it.first != ID(mem2reg))
reg->attributes.emplace(it.first, it.second->clone());
reg->filename = node->filename;
reg->linenum = node->linenum;
children.push_back(reg);

4
passes/equiv/equiv_make.cc
View file

@ -532,10 +532,10 @@ struct EquivMakePass : public Pass {
log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str());
if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
worker.read_blacklists();
worker.read_encfiles();

15
techlibs/ecp5/cells_sim.v
View file

@ -17,10 +17,12 @@ endmodule
// ---------------------------------------
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry *) input CIN,
(* abc_carry *)
input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry *) output COUT
(* abc_carry *)
output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
@ -109,9 +111,12 @@ endmodule
// ---------------------------------------
//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
(* abc_scc_break *) input [3:0] DI,
(* abc_scc_break *) input [3:0] WAD,
(* abc_scc_break *) input WRE,
(* abc_scc_break *)
input [3:0] DI,
(* abc_scc_break *)
input [3:0] WAD,
(* abc_scc_break *)
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO

6
techlibs/ice40/cells_sim.v
View file

@ -143,11 +143,13 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
(* abc_carry *)
output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
(* abc_carry *)
input CI
);
SB_CARRY carry (
.I0(A),

24
techlibs/xilinx/cells_sim.v
View file

@ -183,9 +183,11 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
(* abc_carry *)
output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
(* abc_carry *)
input CI,
input CYINIT,
input [3:0] DI, S
);
@ -298,9 +300,11 @@ endmodule
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -318,9 +322,11 @@ endmodule
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -338,9 +344,11 @@ endmodule
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;

1
tests/various/mem2reg.ys
View file

@ -11,3 +11,4 @@ proc
cd top
select -assert-count 1 m:data1 a:src=<<EOT:4 %i
select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
select -assert-none a:mem2reg