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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl

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Eddie Hung 2019-08-23 11:32:44 -07:00
commit 78b7d8f531
9 changed files with 43 additions and 20 deletions
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24
techlibs/xilinx/cells_sim.v
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@ -183,9 +183,11 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
(* abc_carry *)
output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
(* abc_carry *)
input CI,
input CYINIT,
input [3:0] DI, S
);
@ -298,9 +300,11 @@ endmodule
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -318,9 +322,11 @@ endmodule
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -338,9 +344,11 @@ endmodule
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* abc_scc_break *)
input D,
input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;