mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Merge pull request #4210 from whitequark/fix-read_verilog-hdlname

Browse source 
read_verilog: correctly format `hdlname` attribute value
This commit is contained in:
Martin Povišer 2024-02-19 16:23:06 +01:00 • committed by GitHub
commit 78b0697d33
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/ast/ast.cc
View file

@ -1820,7 +1820,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
AstNode *new_ast = ast->clone(); AstNode *new_ast = ast->clone();
if (!new_ast->attributes.count(ID::hdlname)) if (!new_ast->attributes.count(ID::hdlname))
new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name)); new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1)));
para_counter = 0; para_counter = 0;
for (auto child : new_ast->children) { for (auto child : new_ast->children) {

2
frontends/ast/simplify.cc
View file

@ -5662,7 +5662,7 @@ std::string AstNode::try_pop_module_prefix() const
if (current_scope.count(new_str)) { if (current_scope.count(new_str)) {
std::string prefix = str.substr(0, pos); std::string prefix = str.substr(0, pos);
auto it = current_scope_ast->attributes.find(ID::hdlname); auto it = current_scope_ast->attributes.find(ID::hdlname);
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix) if ((it != current_scope_ast->attributes.end() && it->second->str == prefix.substr(1))
|| prefix == current_scope_ast->str) || prefix == current_scope_ast->str)
return new_str; return new_str;
} }