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Merge af8e85b7d2 into 6378ba10eb

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Dave Anderson 2025-05-07 19:45:26 -07:00 • committed by GitHub
commit 788a50b679
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2 changed files with 22 additions and 3 deletions
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4
techlibs/lattice/cells_bb_ecp5.v
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@ -19,6 +19,8 @@ endmodule
(* blackbox *)
module DP16KD (...);
parameter CLKAMUX = "CLKA";
parameter CLKBMUX = "CLKB";
parameter DATA_WIDTH_A = 18;
parameter DATA_WIDTH_B = 18;
parameter REGMODE_A = "NOREG";
@ -215,6 +217,8 @@ endmodule
(* blackbox *)
module PDPW16KD (...);
parameter CLKRMUX = "CLKR";
parameter CLKWMUX = "CLKW";
parameter DATA_WIDTH_W = 36;
parameter DATA_WIDTH_R = 36;
parameter GSR = "ENABLED";

21
techlibs/lattice/cells_xtra.py
View file

@ -11,10 +11,11 @@ import re
class Cell:
def __init__(self, name, keep=False, port_attrs={}):
def __init__(self, name, keep=False, port_attrs={}, extra_params={}):
self.name = name
self.keep = keep
self.port_attrs = port_attrs
self.extra_params = extra_params
self.found = False
class State(Enum):
@ -120,8 +121,18 @@ devices = [
#Cell("XOR3"),
#Cell("XOR4"),
#Cell("XOR5"),
Cell("DP16KD"),
Cell("PDPW16KD"),
Cell("DP16KD", extra_params={
# Optional clock inverters, present in prjtrellis data but
# not in Diamond bb models.
"CLKAMUX": "CLKA",
"CLKBMUX": "CLKB",
}),
Cell("PDPW16KD", extra_params={
# Optional clock inverters, present in prjtrellis data but
# not in Diamond bb models.
"CLKWMUX": "CLKW",
"CLKRMUX": "CLKR",
}),
#Cell("DPR16X4C"),
#Cell("SPR16X4C"),
#Cell("LVDSOB"),
@ -795,6 +806,10 @@ def xtract_cells_decl(device, cells, dirs, outf):
rng = None
module_ports.append((kind, rng, port))
elif l.startswith('parameter ') and state == State.IN_MODULE:
if cell.extra_params:
for name, default in sorted(cell.extra_params.items()):
outf.write(' parameter {} = "{}";\n'.format(name, default))
cell.extra_params = None
l = l.strip()
if l.endswith((';', ',')):
l = l[:-1]