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Refactor SF2 iobuf insertion, Add clkint insertion

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-03-06 00:41:02 -08:00
parent b1b9edf5cc
commit 78762316aa
4 changed files with 153 additions and 84 deletions
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2
examples/igloo2/runme.sh
View file

@ -1,6 +1,6 @@
#!/bin/bash #!/bin/bash
set -ex set -ex
yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
cp proj/designer/example/export/example.stp . cp proj/designer/example/export/example.stp .

7
techlibs/sf2/cells_sim.v
View file

@ -74,6 +74,13 @@ module CFG4 (
assign Y = INIT >> {D, C, B, A}; assign Y = INIT >> {D, C, B, A};
endmodule endmodule
module CLKINT (
input A,
output Y
);
assign Y = A;
endmodule
module CLKBUF ( module CLKBUF (
input PAD, input PAD,
output Y output Y

140
techlibs/sf2/sf2_iobs.cc
View file

@ -23,42 +23,8 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct Sf2IobsPass : public Pass { static void handle_iobufs(Module *module, bool clkbuf_mode)
Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { } {
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" sf2_iobs [options] [selection]\n");
log("\n");
log("Add SF2 I/O buffers to top module IOs as needed.\n");
log("\n");
log(" -noclkbuf\n");
log(" Do not insert clock buffers\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
bool noclkbuf_mode = false;
log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-noclkbuf") {
noclkbuf_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
Module *module = design->top_module();
if (module == nullptr)
log_cmd_error("No top module found.\n");
SigMap sigmap(module); SigMap sigmap(module);
pool<SigBit> clk_bits; pool<SigBit> clk_bits;
@ -68,11 +34,13 @@ struct Sf2IobsPass : public Pass {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "\\SLE") { if (clkbuf_mode && cell->type == "\\SLE") {
for (auto bit : sigmap(cell->getPort("\\CLK"))) for (auto bit : sigmap(cell->getPort("\\CLK")))
clk_bits.insert(bit); clk_bits.insert(bit);
} }
if (cell->type.in("\\INBUF", "\\OUTBUF", "\\CLKBUF")) { if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUF_DIFF", "\\CLKBUF_DIFF",
"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
for (auto bit : sigmap(cell->getPort("\\PAD"))) for (auto bit : sigmap(cell->getPort("\\PAD")))
handled_io_bits.insert(bit); handled_io_bits.insert(bit);
} }
@ -99,7 +67,7 @@ struct Sf2IobsPass : public Pass {
if (wire->port_output) { if (wire->port_output) {
buf_type = "\\OUTBUF"; buf_type = "\\OUTBUF";
buf_port = "\\D"; buf_port = "\\D";
} else if (clk_bits.count(canonical_bit) && !noclkbuf_mode) { } else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
buf_type = "\\CLKBUF"; buf_type = "\\CLKBUF";
buf_port = "\\Y"; buf_port = "\\Y";
} else { } else {
@ -129,6 +97,100 @@ struct Sf2IobsPass : public Pass {
for (auto &it : pad_bits) for (auto &it : pad_bits)
it.first->setPort("\\PAD", it.second); it.first->setPort("\\PAD", it.second);
}
static void handle_clkint(Module *module)
{
SigMap sigmap(module);
pool<SigBit> clk_bits;
vector<SigBit> handled_clk_bits;
for (auto cell : module->cells())
{
if (cell->type == "\\SLE") {
for (auto bit : sigmap(cell->getPort("\\CLK")))
clk_bits.insert(bit);
}
if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
"\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
for (auto bit : sigmap(cell->getPort("\\Y")))
handled_clk_bits.push_back(bit);
}
}
for (auto bit : handled_clk_bits)
clk_bits.erase(bit);
for (auto cell : vector<Cell*>(module->cells()))
for (auto &conn : cell->connections())
{
if (!cell->output(conn.first))
continue;
SigSpec sig = conn.second;
bool did_something = false;
for (auto &bit : sig) {
SigBit canonical_bit = sigmap(bit);
if (clk_bits.count(canonical_bit)) {
Cell *c = module->addCell(NEW_ID, "\\CLKINT");
SigBit new_bit = module->addWire(NEW_ID);
c->setPort("\\A", new_bit);
c->setPort("\\Y", bit);
log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit));
clk_bits.erase(canonical_bit);
did_something = true;
bit = new_bit;
}
}
if (did_something)
cell->setPort(conn.first, sig);
}
for (auto bit : clk_bits)
log_error("Failed to insert CLKINT for clock signal %s.\n", log_signal(bit));
}
struct Sf2IobsPass : public Pass {
Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" sf2_iobs [options] [selection]\n");
log("\n");
log("Add SF2 I/O buffers and global buffers to top module as needed.\n");
log("\n");
log(" -clkbuf\n");
log(" Insert PAD->global_net clock buffers\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
bool clkbuf_mode = false;
log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-clkbuf") {
clkbuf_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
Module *module = design->top_module();
if (module == nullptr)
log_cmd_error("No top module found.\n");
handle_iobufs(module, clkbuf_mode);
handle_clkint(module);
} }
} Sf2IobsPass; } Sf2IobsPass;

14
techlibs/sf2/synth_sf2.cc
View file

@ -63,8 +63,8 @@ struct SynthSf2Pass : public ScriptPass
log(" -noiobs\n"); log(" -noiobs\n");
log(" run synthesis in \"block mode\", i.e. do not insert IO buffers\n"); log(" run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
log("\n"); log("\n");
log(" -noclkbuf\n"); log(" -clkbuf\n");
log(" do not inser clock buffers, only simpe IO buffers\n"); log(" insert direct PAD->global_net buffers\n");
log("\n"); log("\n");
log(" -retime\n"); log(" -retime\n");
log(" run 'abc' with -dff option\n"); log(" run 'abc' with -dff option\n");
@ -87,7 +87,7 @@ struct SynthSf2Pass : public ScriptPass
flatten = true; flatten = true;
retime = false; retime = false;
iobs = true; iobs = true;
clkbuf = true; clkbuf = false;
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -134,8 +134,8 @@ struct SynthSf2Pass : public ScriptPass
iobs = false; iobs = false;
continue; continue;
} }
if (args[argidx] == "-noclkbuf") { if (args[argidx] == "-clkbuf") {
clkbuf = false; clkbuf = true;
continue; continue;
} }
break; break;
@ -210,9 +210,9 @@ struct SynthSf2Pass : public ScriptPass
if (check_label("map_iobs")) if (check_label("map_iobs"))
{ {
if (help_mode) if (help_mode)
run("sf2_iobs [-noclkbuf]", "(unless -noiobs)"); run("sf2_iobs [-clkbuf]", "(unless -noiobs)");
else if (iobs) else if (iobs)
run(clkbuf ? "sf2_iobs" : "sf2_iobs -noclkbuf"); run(clkbuf ? "sf2_iobs -clkbuf" : "sf2_iobs");
run("clean"); run("clean");
} }