mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-20 01:03:21 +00:00
Code Activity

verific: remove redundant code

Browse source
This commit is contained in:
Dhaval Chaudhari 2026-01-02 14:46:36 +05:30
parent afe6d4092e
commit 78720b9ba2
1 changed files with 4 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

14
frontends/verific/verific.cc
View file

@ -3078,9 +3078,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (verific_opt) {
log(" Running Verific optimizations for %s.\n", it->first.c_str());
// log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
// nl->InferClockEnableMux();
log(" Running post-elaboration for %s.\n", it->first.c_str());
nl->PostElaborationProcess();
@ -3706,17 +3703,14 @@ struct VerificPass : public Pass {
veri_file::AddLOption(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-optimization") {
verific_opt = true;
continue;
}
#endif
break;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (args[argidx] == "-optimization") {
verific_opt = true;
continue;
}
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{