mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-10 16:13:26 +00:00
Code Activity

Merge pull request #2197 from Xiretza/test_cell-shifts

Browse source 
test_cell: don't generate directional shifts with \B_SIGNED=1
This commit is contained in:
whitequark 2020-06-29 12:34:09 +00:00 • committed by GitHub
commit 7860fb628f
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/tests/test_cell.cc
View file

@ -264,6 +264,10 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
} }
if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
cell->parameters[ID::B_SIGNED] = false;
}
if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));