mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
rtlil: represent Const strings as std::string
This commit is contained in:
parent
61ed9b6263
commit
785bd44da7
90 changed files with 947 additions and 643 deletions
|
@ -80,7 +80,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
|
|||
for (int j = 0; j < GetSize(select.second); j++)
|
||||
if (i & 1 << idx_sel[j])
|
||||
sel_lut_idx |= 1 << j;
|
||||
bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
|
||||
bool select_val = (select.first[sel_lut_idx] == State::S1);
|
||||
bool new_bit;
|
||||
if (select_val ^ select_inv) {
|
||||
// Use alt_data.
|
||||
|
@ -91,9 +91,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
|
|||
} else {
|
||||
// Use original LUT.
|
||||
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
|
||||
new_bit = data.first.bits[lut_idx] == State::S1;
|
||||
new_bit = data.first[lut_idx] == State::S1;
|
||||
}
|
||||
result.first.bits[i] = new_bit ? State::S1 : State::S0;
|
||||
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue