mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

rtlil: represent Const strings as std::string

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -82,7 +82,7 @@ struct FoldInvWorker {
Const result(State::S0, GetSize(lut));
for (int i = 0; i < GetSize(lut); i++) {
int j = i ^ (1 << bit);
result[j] = lut[i];
result.bits()[j] = lut[i];
}
return result;
}
@ -91,7 +91,7 @@ struct FoldInvWorker {
{
Const result(State::S0, GetSize(lut));
for (int i = 0; i < GetSize(lut); i++)
result[i] = (lut[i] == State::S1) ? State::S0 : State::S1;
result.bits()[i] = (lut[i] == State::S1) ? State::S0 : State::S1;
return result;
}

16
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -35,10 +35,10 @@ void invert_gp_dff(Cell *cell, bool invert_input)
{
Const initval = cell->getParam(ID::INIT);
if (GetSize(initval) >= 1) {
if (initval.bits[0] == State::S0)
initval.bits[0] = State::S1;
else if (initval.bits[0] == State::S1)
initval.bits[0] = State::S0;
if (initval[0] == State::S0)
initval.bits()[0] = State::S1;
else if (initval[0] == State::S1)
initval.bits()[0] = State::S0;
cell->setParam(ID::INIT, initval);
}
@ -46,10 +46,10 @@ void invert_gp_dff(Cell *cell, bool invert_input)
{
Const srmode = cell->getParam(ID(SRMODE));
if (GetSize(srmode) >= 1) {
if (srmode.bits[0] == State::S0)
srmode.bits[0] = State::S1;
else if (srmode.bits[0] == State::S1)
srmode.bits[0] = State::S0;
if (srmode[0] == State::S0)
srmode.bits()[0] = State::S1;
else if (srmode[0] == State::S1)
srmode.bits()[0] = State::S0;
cell->setParam(ID(SRMODE), srmode);
}
}

6
techlibs/microchip/microchip_dffopt.cc
View file

@ -80,7 +80,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
for (int j = 0; j < GetSize(select.second); j++)
if (i & 1 << idx_sel[j])
sel_lut_idx |= 1 << j;
bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
bool select_val = (select.first[sel_lut_idx] == State::S1);
bool new_bit;
if (select_val ^ select_inv) {
// Use alt_data.
@ -91,9 +91,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
} else {
// Use original LUT.
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first.bits[lut_idx] == State::S1;
new_bit = data.first[lut_idx] == State::S1;
}
result.first.bits[i] = new_bit ? State::S1 : State::S0;
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
}
return true;
}

10
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -60,7 +60,7 @@ struct QlDspSimdPass : public Pass {
// ..........................................
const int m_ModeBitsSize = 80;
const size_t m_ModeBitsSize = 80;
// DSP parameters
const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
@ -176,7 +176,7 @@ struct QlDspSimdPass : public Pass {
sigspec.append(sig);
}
int padding = width / 2 - sigspec.bits().size();
int padding = width / 2 - sigspec.size();
if (padding) {
if (!isOutput)
@ -200,8 +200,10 @@ struct QlDspSimdPass : public Pass {
auto val_a = dsp_a->getParam(it);
auto val_b = dsp_b->getParam(it);
mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end());
mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end());
mode_bits.bits().insert(mode_bits.bits().end(),
val_a.begin(), val_a.end());
mode_bits.bits().insert(mode_bits.bits().end(),
val_b.begin(), val_b.end());
}
// Enable the fractured mode by connecting the control

8
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -79,7 +79,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
for (int j = 0; j < GetSize(select.second); j++)
if (i & 1 << idx_sel[j])
sel_lut_idx |= 1 << j;
bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
bool select_val = (select.first[sel_lut_idx] == State::S1);
bool new_bit;
if (select_val ^ select_inv) {
// Use alt_data.
@ -90,9 +90,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
} else {
// Use original LUT.
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first.bits[lut_idx] == State::S1;
new_bit = data.first[lut_idx] == State::S1;
}
result.first.bits[i] = new_bit ? State::S1 : State::S0;
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
}
return true;
}
@ -212,7 +212,7 @@ lut_sigin_done:
if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
// Flip all bits in the LUT.
for (int i = 0; i < GetSize(lut_d.first); i++)
lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
lut_d.first.bits()[i] = (lut_d.first[i] == State::S1) ? State::S0 : State::S1;
}
LutData lut_d_post_ce;