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https://github.com/YosysHQ/yosys
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rtlil: represent Const strings as std::string
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parent
61ed9b6263
commit
785bd44da7
90 changed files with 947 additions and 643 deletions
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@ -1217,7 +1217,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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auto Qi = initmap(Q);
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auto it = Qi.wire->attributes.find(ID::init);
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if (it != Qi.wire->attributes.end())
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it->second[Qi.offset] = State::Sx;
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it->second.bits()[Qi.offset] = State::Sx;
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}
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else if (cell->type.in(ID($_AND_), ID($_NOT_)))
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module->remove(cell);
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@ -1528,7 +1528,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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int i = 0;
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while (i < GetSize(mask)) {
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for (int j = 0; j < (1 << index); j++)
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std::swap(mask[i+j], mask[i+j+(1 << index)]);
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std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]);
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i += 1 << (index+1);
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}
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A[index] = y_bit;
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@ -1543,7 +1543,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
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// and get cleaned away
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clone_lut:
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driver_mask = driver_lut->getParam(ID::LUT);
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for (auto &b : driver_mask.bits) {
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for (auto &b : driver_mask.bits()) {
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if (b == RTLIL::State::S0) b = RTLIL::State::S1;
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else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
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}
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@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
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for (int i = 0; i < GetSize(sig); i++) {
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if (initval[i] == State::Sx)
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continue;
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while (GetSize(value.bits) <= i)
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value.bits.push_back(State::S0);
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if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
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while (GetSize(value) <= i)
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value.bits().push_back(State::S0);
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if (noreinit && value[i] != State::Sx && value[i] != initval[i])
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log_error("Trying to assign a different init value for %s.%s.%s which technically "
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"have a conflicted init value.\n",
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log_id(module), log_id(cell), log_id(it.second));
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value.bits[i] = initval[i];
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value.bits()[i] = initval[i];
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}
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if (highlow_mode && GetSize(value) != 0) {
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@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
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if (ff.has_arst) {
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if (ff.val_arst[i] == State::Sx) {
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if (!(supported & (mask << 8)))
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ff.val_arst[i] = State::S0;
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ff.val_arst.bits()[i] = State::S0;
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if (!(supported & (mask << 4)))
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ff.val_arst[i] = State::S1;
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ff.val_arst.bits()[i] = State::S1;
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}
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}
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if (ff.has_srst) {
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if (ff.val_srst[i] == State::Sx) {
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if (!(supported & (mask << 8)))
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ff.val_srst[i] = State::S0;
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ff.val_srst.bits()[i] = State::S0;
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if (!(supported & (mask << 4)))
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ff.val_srst[i] = State::S1;
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ff.val_srst.bits()[i] = State::S1;
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}
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}
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}
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@ -1399,7 +1399,7 @@ struct FlowmapWorker
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log_signal(node), log_signal(undef), env.c_str());
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}
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lut_table[i] = value.as_bool() ? State::S1 : State::S0;
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lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0;
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ce.pop();
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}
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@ -684,7 +684,7 @@ struct TechmapWorker
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for (auto &bit : sigmap(conn.second)) {
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int val = unique_bit_id.at(bit);
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for (int i = 0; i < bits; i++) {
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value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
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value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
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val = val >> 1;
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}
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}
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@ -1226,7 +1226,7 @@ struct TechmapPass : public Pass {
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dict<IdString, pool<IdString>> celltypeMap;
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for (auto module : map->modules()) {
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if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
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if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).empty()) {
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char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
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for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) {
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std::vector<std::string> queue;
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@ -73,10 +73,10 @@ struct ZinitPass : public Pass {
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pool<int> bits;
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for (int i = 0; i < ff.width; i++) {
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if (ff.val_init.bits[i] == State::S1)
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if (ff.val_init[i] == State::S1)
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bits.insert(i);
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else if (ff.val_init.bits[i] != State::S0 && all_mode)
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ff.val_init.bits[i] = State::S0;
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else if (ff.val_init[i] != State::S0 && all_mode)
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ff.val_init.bits()[i] = State::S0;
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}
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ff.flip_bits(bits);
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ff.emit();
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