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rtlil: represent Const strings as std::string

This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions

View file

@ -1217,7 +1217,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end())
it->second[Qi.offset] = State::Sx;
it->second.bits()[Qi.offset] = State::Sx;
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);
@ -1528,7 +1528,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
int i = 0;
while (i < GetSize(mask)) {
for (int j = 0; j < (1 << index); j++)
std::swap(mask[i+j], mask[i+j+(1 << index)]);
std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]);
i += 1 << (index+1);
}
A[index] = y_bit;
@ -1543,7 +1543,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits) {
for (auto &b : driver_mask.bits()) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}

View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx)
continue;
while (GetSize(value.bits) <= i)
value.bits.push_back(State::S0);
if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
while (GetSize(value) <= i)
value.bits().push_back(State::S0);
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second));
value.bits[i] = initval[i];
value.bits()[i] = initval[i];
}
if (highlow_mode && GetSize(value) != 0) {

View file

@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
if (ff.has_arst) {
if (ff.val_arst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_arst[i] = State::S0;
ff.val_arst.bits()[i] = State::S0;
if (!(supported & (mask << 4)))
ff.val_arst[i] = State::S1;
ff.val_arst.bits()[i] = State::S1;
}
}
if (ff.has_srst) {
if (ff.val_srst[i] == State::Sx) {
if (!(supported & (mask << 8)))
ff.val_srst[i] = State::S0;
ff.val_srst.bits()[i] = State::S0;
if (!(supported & (mask << 4)))
ff.val_srst[i] = State::S1;
ff.val_srst.bits()[i] = State::S1;
}
}
}

View file

@ -1399,7 +1399,7 @@ struct FlowmapWorker
log_signal(node), log_signal(undef), env.c_str());
}
lut_table[i] = value.as_bool() ? State::S1 : State::S0;
lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0;
ce.pop();
}

View file

@ -684,7 +684,7 @@ struct TechmapWorker
for (auto &bit : sigmap(conn.second)) {
int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) {
value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1;
}
}
@ -1226,7 +1226,7 @@ struct TechmapPass : public Pass {
dict<IdString, pool<IdString>> celltypeMap;
for (auto module : map->modules()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).empty()) {
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n")) {
std::vector<std::string> queue;

View file

@ -73,10 +73,10 @@ struct ZinitPass : public Pass {
pool<int> bits;
for (int i = 0; i < ff.width; i++) {
if (ff.val_init.bits[i] == State::S1)
if (ff.val_init[i] == State::S1)
bits.insert(i);
else if (ff.val_init.bits[i] != State::S0 && all_mode)
ff.val_init.bits[i] = State::S0;
else if (ff.val_init[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0;
}
ff.flip_bits(bits);
ff.emit();