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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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6
passes/sat/formalff.cc
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@ -363,7 +363,7 @@ struct PropagateWorker
for (auto wire : module->wires())
if (wire->has_attribute(ID::replaced_by_gclk))
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false);
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
@ -622,7 +622,7 @@ struct FormalFfPass : public Pass {
auto before = ff.val_init;
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
ff.val_init[i] = State::S0;
ff.val_init.bits()[i] = State::S0;
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
@ -745,7 +745,7 @@ struct FormalFfPass : public Pass {
for (auto wire : module->wires()) {
if (!wire->has_attribute(ID::replaced_by_gclk))
continue;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].at(0) == State::S1;
found.emplace_back(SigSpec(wire), clk_pol);
}