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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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8
passes/sat/eval.cc
View file

@ -250,13 +250,13 @@ struct VlogHammerReporter
std::string module_name = module_names[mod].c_str();
ConstEval ce(module);
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
std::vector<RTLIL::State> bits(patterns[idx].begin(), patterns[idx].begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
RTLIL::Wire *wire = module->wire(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits.push_back(bits.back());
recorded_set_vals.bits().push_back(bits.back());
bits.pop_back();
}
if (module == modules.front()) {
@ -346,7 +346,7 @@ struct VlogHammerReporter
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits)
for (auto &bit : patterns.back().bits())
if (bit == RTLIL::State::S0)
bit = RTLIL::State::S1;
else if (bit == RTLIL::State::S1)
@ -557,7 +557,7 @@ struct EvalPass : public Pass {
tab_line.clear();
ce.pop();
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.bits.size());
tabvals = RTLIL::const_add(tabvals, RTLIL::Const(1), false, false, tabvals.size());
}
while (tabvals.as_bool());

2
passes/sat/expose.cc
View file

@ -131,7 +131,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).to_bits();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
info.arst_value = arst_value.at(i);

6
passes/sat/formalff.cc
View file

@ -363,7 +363,7 @@ struct PropagateWorker
for (auto wire : module->wires())
if (wire->has_attribute(ID::replaced_by_gclk))
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1, false);
replace_clk_bit(SigBit(wire), wire->attributes[ID::replaced_by_gclk].at(0) == State::S1, false);
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
@ -622,7 +622,7 @@ struct FormalFfPass : public Pass {
auto before = ff.val_init;
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
ff.val_init[i] = State::S0;
ff.val_init.bits()[i] = State::S0;
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
@ -745,7 +745,7 @@ struct FormalFfPass : public Pass {
for (auto wire : module->wires()) {
if (!wire->has_attribute(ID::replaced_by_gclk))
continue;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].bits.at(0) == State::S1;
bool clk_pol = wire->attributes[ID::replaced_by_gclk].at(0) == State::S1;
found.emplace_back(SigSpec(wire), clk_pol);
}

16
passes/sat/sat.cc
View file

@ -629,9 +629,9 @@ struct SatHelper
bool found_undef = false;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx, found_undef = true;
value.bits().back() = RTLIL::State::Sx, found_undef = true;
}
if (info.timestep != last_timestep) {
@ -740,9 +740,9 @@ struct SatHelper
RTLIL::Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
if (info.timestep != last_timestep) {
@ -754,11 +754,11 @@ struct SatHelper
}
if(info.width == 1) {
fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str());
fprintf(f, "%c%s\n", bitvals[value[0]], vcdnames[info.description].c_str());
} else {
fprintf(f, "b");
for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD
fprintf(f, "%c", bitvals[value.bits[k]]);
fprintf(f, "%c", bitvals[value[k]]);
fprintf(f, " %s\n", vcdnames[info.description].c_str());
}
}
@ -786,9 +786,9 @@ struct SatHelper
{
Const value;
for (int i = 0; i < info.width; i++) {
value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits.back() = RTLIL::State::Sx;
value.bits().back() = RTLIL::State::Sx;
}
wavedata[info.description].first = info.width;

34
passes/sat/sim.cc
View file

@ -135,7 +135,7 @@ void zinit(State &v)
void zinit(Const &v)
{
for (auto &bit : v.bits)
for (auto &bit : v.bits())
zinit(bit);
}
@ -423,11 +423,11 @@ struct SimInstance
for (auto bit : sigmap(sig))
if (bit.wire == nullptr)
value.bits.push_back(bit.data);
value.bits().push_back(bit.data);
else if (state_nets.count(bit))
value.bits.push_back(state_nets.at(bit));
value.bits().push_back(state_nets.at(bit));
else
value.bits.push_back(State::Sz);
value.bits().push_back(State::Sz);
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
@ -486,9 +486,9 @@ struct SimInstance
int offset = (addr - state.mem->start_offset) * state.mem->width;
for (int i = 0; i < GetSize(data); i++)
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data.bits[i] != State::Sa)
if (state.data.bits[i+offset] != data.bits[i])
dirty = true, state.data.bits[i+offset] = data.bits[i];
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa)
if (state.data[i+offset] != data[i])
dirty = true, state.data.bits()[i+offset] = data[i];
if (dirty)
dirty_memories.insert(memid);
@ -499,8 +499,8 @@ struct SimInstance
auto &state = mem_database[memid];
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data.bits[offset] != data) {
state.data.bits[offset] = data;
if (state.data[offset] != data) {
state.data.bits()[offset] = data;
dirty_memories.insert(memid);
}
}
@ -717,10 +717,10 @@ struct SimInstance
for(int i=0;i<ff.past_d.size();i++) {
if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
current_q[i] = State::S0;
current_q.bits()[i] = State::S0;
}
else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
current_q[i] = State::S1;
current_q.bits()[i] = State::S1;
}
}
}
@ -769,8 +769,8 @@ struct SimInstance
int index = addr_int - mem.start_offset;
if (index >= 0 && index < mem.size)
for (int i = 0; i < (mem.width << port.wide_log2); i++)
if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) {
mdb.data.bits.at(index*mem.width+i) = data[i];
if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) {
mdb.data.bits().at(index*mem.width+i) = data[i];
dirty_memories.insert(mem.memid);
did_something = true;
}
@ -971,7 +971,7 @@ struct SimInstance
if (w->attributes.count(ID::init) == 0)
w->attributes[ID::init] = Const(State::Sx, GetSize(w));
w->attributes[ID::init][sig_q[i].offset] = initval[i];
w->attributes[ID::init].bits()[sig_q[i].offset] = initval[i];
}
}
@ -2542,7 +2542,7 @@ struct AIWWriter : public OutputWriter
{
auto val = it.second ? State::S1 : State::S0;
SigBit bit = aiw_inputs.at(it.first);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == val)
skip = true;
}
@ -2552,7 +2552,7 @@ struct AIWWriter : public OutputWriter
{
if (aiw_inputs.count(i)) {
SigBit bit = aiw_inputs.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else
@ -2561,7 +2561,7 @@ struct AIWWriter : public OutputWriter
}
if (aiw_inits.count(i)) {
SigBit bit = aiw_inits.at(i);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
auto v = current[mapping[bit.wire]].at(bit.offset);
if (v == State::S1)
aiwfile << '1';
else