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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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6
passes/proc/proc_init.cc
View file

@ -53,11 +53,11 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
while (GetSize(wireinit) < lhs_c.wire->width)
wireinit.bits().push_back(State::Sx);
for (int i = 0; i < lhs_c.width; i++) {
auto &initbit = wireinit.bits[i + lhs_c.offset];
auto &initbit = wireinit.bits()[i + lhs_c.offset];
if (initbit != State::Sx && initbit != value[i])
log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
initbit = value[i];

2
passes/proc/proc_memwr.cc
View file

@ -39,7 +39,7 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
Const priority_mask(State::S0, port_id);
for (int i = 0; i < GetSize(prev_port_ids); i++)
if (memwr.priority_mask[i] == State::S1)
priority_mask[prev_port_ids[i]] = State::S1;
priority_mask.bits()[prev_port_ids[i]] = State::S1;
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));

16
passes/proc/proc_rom.cc
View file

@ -97,10 +97,10 @@ struct RomWorker
log_debug("rejecting switch: lhs not uniform\n");
return;
}
val[it2->second] = it.second[i].data;
val.bits()[it2->second] = it.second[i].data;
}
}
for (auto bit: val.bits) {
for (auto bit: val) {
if (bit == State::Sm) {
log_debug("rejecting switch: lhs not uniform\n");
return;
@ -113,8 +113,8 @@ struct RomWorker
return;
}
Const c = addr.as_const();
while (GetSize(c) && c.bits.back() == State::S0)
c.bits.pop_back();
while (GetSize(c) && c.back() == State::S0)
c.bits().pop_back();
if (GetSize(c) > swsigbits)
continue;
if (GetSize(c) > 30) {
@ -160,11 +160,11 @@ struct RomWorker
auto it = vals.find(i);
if (it == vals.end()) {
log_assert(got_default);
for (auto bit: default_val.bits)
init_data.bits.push_back(bit);
for (auto bit: default_val)
init_data.bits().push_back(bit);
} else {
for (auto bit: it->second.bits)
init_data.bits.push_back(bit);
for (auto bit: it->second)
init_data.bits().push_back(bit);
}
}