mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-16 06:31:29 +00:00
Code Activity

rtlil: represent Const strings as std::string

Browse source
This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/memory/memory_bram.cc
View file

@ -848,9 +848,9 @@ grow_read_ports:;
for (int i = 0; i < mem.width; i++)
if (shuffle_map[i] != -1) {
module->connect(port.data[shuffle_map[i]], new_data[i]);
new_init_value[i] = port.init_value[shuffle_map[i]];
new_arst_value[i] = port.arst_value[shuffle_map[i]];
new_srst_value[i] = port.srst_value[shuffle_map[i]];
new_init_value.bits()[i] = port.init_value[shuffle_map[i]];
new_arst_value.bits()[i] = port.arst_value[shuffle_map[i]];
new_srst_value.bits()[i] = port.srst_value[shuffle_map[i]];
}
port.data = new_data;
port.init_value = new_init_value;
@ -887,9 +887,9 @@ grow_read_ports:;
for (int i = 0; i < init_size; i++)
for (int j = 0; j < bram.dbits; j++)
if (init_offset+i < GetSize(initdata) && init_offset+i >= 0)
initparam[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
initparam.bits()[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j];
else
initparam[i*bram.dbits+j] = State::Sx;
initparam.bits()[i*bram.dbits+j] = State::Sx;
c->setParam(ID::INIT, initparam);
}

10
passes/memory/memory_libmap.cc
View file

@ -1019,7 +1019,7 @@ void MemMapping::handle_priority() {
}
bool is_all_zero(const Const &val) {
for (auto bit: val.bits)
for (auto bit: val)
if (bit == State::S1)
return false;
return true;
@ -1913,7 +1913,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(val.bits[bit.bit]);
hw_val.push_back(val[bit.bit]);
}
}
if (pdef.rdinitval == ResetValKind::NoUndef)
@ -1926,7 +1926,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.arst_value.bits[bit.bit]);
hw_val.push_back(rport.arst_value[bit.bit]);
}
}
if (pdef.rdarstval == ResetValKind::NoUndef)
@ -1939,7 +1939,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
if (!bit.valid) {
hw_val.push_back(State::Sx);
} else {
hw_val.push_back(rport.srst_value.bits[bit.bit]);
hw_val.push_back(rport.srst_value[bit.bit]);
}
}
if (pdef.rdsrstval == ResetValKind::NoUndef)
@ -2103,7 +2103,7 @@ void MemMapping::emit(const MemConfig &cfg) {
if (hwa & 1 << i)
addr += 1 << hw_addr_swizzle[i];
if (addr >= mem.start_offset && addr < mem.start_offset + mem.size)
initval.push_back(init_data.bits[(addr - mem.start_offset) * mem.width + bit.bit]);
initval.push_back(init_data[(addr - mem.start_offset) * mem.width + bit.bit]);
else
initval.push_back(State::Sx);
}

4
passes/memory/memory_share.cc
View file

@ -60,11 +60,11 @@ struct MemoryShareWorker
bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) {
res = Const(State::Sx, mem.width << wide_log2);
for (int i = 0; i < GetSize(src1); i++)
res[i + sub1 * mem.width] = src1[i];
res.bits()[i + sub1 * mem.width] = src1[i];
for (int i = 0; i < GetSize(src2); i++) {
if (src2[i] == State::Sx)
continue;
auto &dst = res[i + sub2 * mem.width];
auto &dst = res.bits()[i + sub2 * mem.width];
if (dst == src2[i])
continue;
if (dst != State::Sx)