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rtlil: represent Const strings as std::string
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parent
61ed9b6263
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90 changed files with 947 additions and 643 deletions
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@ -219,7 +219,7 @@ struct IFExpander
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const RTLIL::SigSpec &conn_signals)
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{
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// Check if the connected wire is a potential interface in the parent module
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std::string interface_name_str = conn_signals.bits()[0].wire->name.str();
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std::string interface_name_str = conn_signals[0].wire->name.str();
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// Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
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interface_name_str.replace(0,23,"");
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interface_name_str = "\\" + interface_name_str;
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@ -289,7 +289,7 @@ struct IFExpander
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return;
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// If the connection looks like an interface, handle it.
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const auto &bits = conn_signals.bits();
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const auto &bits = conn_signals;
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if (bits.size() == 1 && bits[0].wire->get_bool_attribute(ID::is_interface))
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on_interface(submodule, conn_name, conn_signals);
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}
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