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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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4
passes/hierarchy/hierarchy.cc
View file

@ -219,7 +219,7 @@ struct IFExpander
const RTLIL::SigSpec &conn_signals)
{
// Check if the connected wire is a potential interface in the parent module
std::string interface_name_str = conn_signals.bits()[0].wire->name.str();
std::string interface_name_str = conn_signals[0].wire->name.str();
// Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
interface_name_str.replace(0,23,"");
interface_name_str = "\\" + interface_name_str;
@ -289,7 +289,7 @@ struct IFExpander
return;
// If the connection looks like an interface, handle it.
const auto &bits = conn_signals.bits();
const auto &bits = conn_signals;
if (bits.size() == 1 && bits[0].wire->get_bool_attribute(ID::is_interface))
on_interface(submodule, conn_name, conn_signals);
}

8
passes/hierarchy/submod.cc
View file

@ -79,7 +79,7 @@ struct SubmodWorker
flag_wire(c.wire, create, set_int_used, set_ext_driven, set_ext_used);
if (set_int_driven)
for (int i = c.offset; i < c.offset+c.width; i++) {
wire_flags.at(c.wire).is_int_driven[i] = State::S1;
wire_flags.at(c.wire).is_int_driven.bits()[i] = State::S1;
flag_found_something = true;
}
}
@ -185,8 +185,8 @@ struct SubmodWorker
auto it = sig[i].wire->attributes.find(ID::init);
if (it != sig[i].wire->attributes.end()) {
auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first;
jt->second[i] = it->second[sig[i].offset];
it->second[sig[i].offset] = State::Sx;
jt->second.bits()[i] = it->second[sig[i].offset];
it->second.bits()[sig[i].offset] = State::Sx;
}
}
}
@ -279,7 +279,7 @@ struct SubmodWorker
for (auto cell : module->cells())
{
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) {
if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].size() == 0) {
cell->attributes.erase(ID::submod);
continue;
}