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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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4
passes/fsm/fsm_extract.cc
View file

@ -168,10 +168,10 @@ undef_bit_in_next_state:
ctrl_in_bit_indices[ctrl_in[i]] = i;
for (auto &it : ctrl_in_bit_indices)
if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
if (tr.ctrl_in.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
for (auto &dc_bit : exclusive_ctrls.at(it.first))
if (ctrl_in_bit_indices.count(dc_bit))
tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
if (state_in >= 0)

30
passes/fsm/fsm_map.cc
View file

@ -30,11 +30,11 @@ PRIVATE_NAMESPACE_BEGIN
static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
{
log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits));
for (int i = 0; i < GetSize(super_pattern.bits); i++)
if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] != sub_pattern.bits[i])
log_assert(GetSize(super_pattern) == GetSize(sub_pattern));
for (int i = 0; i < GetSize(super_pattern); i++)
if (sub_pattern[i] == RTLIL::State::S0 || sub_pattern[i] == RTLIL::State::S1) {
if (super_pattern[i] == RTLIL::State::S0 || super_pattern[i] == RTLIL::State::S1) {
if (super_pattern[i] != sub_pattern[i])
return false;
} else
return false;
@ -54,10 +54,10 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Const pattern = it.first;
RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
for (size_t j = 0; j < pattern.bits.size(); j++)
if (pattern.bits[j] == RTLIL::State::S0 || pattern.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < pattern.size(); j++)
if (pattern[j] == RTLIL::State::S0 || pattern[j] == RTLIL::State::S1) {
eq_sig_a.append(ctrl_in.extract(j, 1));
eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
eq_sig_b.append(RTLIL::SigSpec(pattern[j]));
}
for (int in_state : it.second)
@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
state_dff->type = ID($adff);
state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits())
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
@ -198,10 +198,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
RTLIL::Const state = fsm_data.state_table[i];
RTLIL::SigSpec sig_a, sig_b;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
for (size_t j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S0 || state[j] == RTLIL::State::S1) {
sig_a.append(RTLIL::SigSpec(state_wire, j));
sig_b.append(RTLIL::SigSpec(state.bits[j]));
sig_b.append(RTLIL::SigSpec(state[j]));
}
if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
@ -261,8 +261,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
RTLIL::Const state = fsm_data.state_table[i];
int bit_idx = -1;
for (size_t j = 0; j < state.bits.size(); j++)
if (state.bits[j] == RTLIL::State::S1)
for (size_t j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S1)
bit_idx = j;
if (bit_idx >= 0)
next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
@ -306,7 +306,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
fullstate_cache.insert(j);
for (auto &tr : fsm_data.transition_table) {
if (tr.ctrl_out.bits[i] == RTLIL::State::S1)
if (tr.ctrl_out[i] == RTLIL::State::S1)
pattern_cache[tr.ctrl_in].insert(tr.state_in);
else
fullstate_cache.erase(tr.state_in);

22
passes/fsm/fsm_opt.cc
View file

@ -106,11 +106,11 @@ struct FsmOpt
for (int i = 0; i < ctrl_in.size(); i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
if (tr.ctrl_in[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in[i]) != ctrl_bit)
goto delete_this_transition;
continue;
}
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1)
if (tr.ctrl_in[i] <= RTLIL::State::S1)
ctrl_in_used[i] = true;
}
new_transition_table.push_back(tr);
@ -169,8 +169,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_in.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_in.bits()[j];
if (si > RTLIL::State::S1)
si = sj;
@ -207,8 +207,8 @@ struct FsmOpt
for (auto tr : fsm_data.transition_table)
{
RTLIL::State &si = tr.ctrl_in.bits[i];
RTLIL::State &sj = tr.ctrl_out.bits[j];
RTLIL::State &si = tr.ctrl_in.bits()[i];
RTLIL::State &sj = tr.ctrl_out.bits()[j];
if (si > RTLIL::State::S1 || si == sj) {
RTLIL::SigSpec tmp(tr.ctrl_in);
@ -232,22 +232,22 @@ struct FsmOpt
for (auto &pattern : set)
{
if (pattern.bits[bit] > RTLIL::State::S1) {
if (pattern[bit] > RTLIL::State::S1) {
new_set.insert(pattern);
continue;
}
RTLIL::Const other_pattern = pattern;
if (pattern.bits[bit] == RTLIL::State::S1)
other_pattern.bits[bit] = RTLIL::State::S0;
if (pattern[bit] == RTLIL::State::S1)
other_pattern.bits()[bit] = RTLIL::State::S0;
else
other_pattern.bits[bit] = RTLIL::State::S1;
other_pattern.bits()[bit] = RTLIL::State::S1;
if (set.count(other_pattern) > 0) {
log(" Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
other_pattern.bits[bit] = RTLIL::State::Sa;
other_pattern.bits()[bit] = RTLIL::State::Sa;
new_set.insert(other_pattern);
did_something = true;
continue;

6
passes/fsm/fsm_recode.cc
View file

@ -43,8 +43,8 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
fprintf(f, "set_fsm_encoding {");
for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
fprintf(f, " s%d=2#", i);
for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
for (int j = GetSize(fsm_data.state_table[i])-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i][j] == RTLIL::State::S1 ? '1' : '0');
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(name).c_str(),
@ -105,7 +105,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
if (encoding == "one-hot") {
new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
new_code.bits[state_idx] = RTLIL::State::S1;
new_code.bits()[state_idx] = RTLIL::State::S1;
} else
if (encoding == "binary") {
new_code = RTLIL::Const(state_idx, fsm_data.state_bits);

26
passes/fsm/fsmdata.h
View file

@ -48,8 +48,8 @@ struct FsmData
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
std::vector<RTLIL::State> &bits_state = state_table[i].bits();
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
@ -57,16 +57,16 @@ struct FsmData
cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++)
{
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits;
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits;
std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits;
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits;
std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
// append lsb first
bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
@ -97,23 +97,23 @@ struct FsmData
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
int off_begin = i*state_bits, off_end = off_begin + state_bits;
state_code.bits.insert(state_code.bits.begin(), state_table.bits.begin()+off_begin, state_table.bits.begin()+off_end);
state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
this->state_table.push_back(state_code);
}
for (int i = 0; i < trans_num; i++)
{
auto off_ctrl_out = trans_table.bits.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
auto off_state_out = off_ctrl_out + num_outputs;
auto off_ctrl_in = off_state_out + state_num_log2;
auto off_state_in = off_ctrl_in + num_inputs;
auto off_end = off_state_in + state_num_log2;
RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
ctrl_out.bits.insert(state_in.bits.begin(), off_ctrl_out, off_state_out);
state_out.bits.insert(state_out.bits.begin(), off_state_out, off_ctrl_in);
ctrl_in.bits.insert(ctrl_in.bits.begin(), off_ctrl_in, off_state_in);
state_in.bits.insert(state_in.bits.begin(), off_state_in, off_end);
ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
transition_t tr;
tr.state_in = state_in.as_int();