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rtlil: represent Const strings as std::string
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parent
61ed9b6263
commit
785bd44da7
90 changed files with 947 additions and 643 deletions
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@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
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{
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for (auto *cell : module->selected_cells()) {
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for (auto ¶meter : cell->parameters) {
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for (auto &bit : parameter.second.bits) {
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for (auto bit : parameter.second) {
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if (bit > RTLIL::State::S1)
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bit = worker.next_bit();
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}
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@ -390,12 +390,12 @@ struct SetundefPass : public Pass {
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for (auto wire : initwires)
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{
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Const &initval = wire->attributes[ID::init];
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initval.bits.resize(GetSize(wire), State::Sx);
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initval.bits().resize(GetSize(wire), State::Sx);
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for (int i = 0; i < GetSize(wire); i++) {
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SigBit bit = sigmap(SigBit(wire, i));
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if (initval[i] == State::Sx && ffbits.count(bit)) {
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initval[i] = worker.next_bit();
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initval.bits()[i] = worker.next_bit();
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ffbits.erase(bit);
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}
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}
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@ -421,7 +421,7 @@ struct SetundefPass : public Pass {
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continue;
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Const &initval = wire->attributes[ID::init];
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initval.bits.resize(GetSize(wire), State::Sx);
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initval.bits().resize(GetSize(wire), State::Sx);
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if (initval.is_fully_undef()) {
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wire->attributes.erase(ID::init);
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