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rtlil: represent Const strings as std::string

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This commit is contained in:
Emil J. Tywoniak 2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
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2
passes/cmds/bugpoint.cc
View file

@ -354,7 +354,7 @@ struct BugpointPass : public Pass {
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
auto &mask = it2->priority_mask;
if (GetSize(mask) > i) {
mask.bits.erase(mask.bits.begin() + i);
mask.bits().erase(mask.bits().begin() + i);
}
}
return design_copy;

2
passes/cmds/clean_zerowidth.cc
View file

@ -160,7 +160,7 @@ struct CleanZeroWidthPass : public Pass {
memwr.address = State::S0;
Const priority_mask;
for (auto x : swizzle) {
priority_mask.bits.push_back(memwr.priority_mask.bits[x]);
priority_mask.bits().push_back(memwr.priority_mask[x]);
}
memwr.priority_mask = priority_mask;
swizzle.push_back(i);

2
passes/cmds/dft_tag.cc
View file

@ -883,7 +883,7 @@ struct DftTagWorker {
{
if (sig_a.is_fully_const()) {
auto const_val = sig_a.as_const();
for (auto &bit : const_val.bits)
for (auto bit : const_val)
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
return const_val;
}

4
passes/cmds/printattrs.cc
View file

@ -40,12 +40,12 @@ struct PrintAttrsPass : public Pass {
}
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags == RTLIL::CONST_FLAG_STRING)
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
else
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override

8
passes/cmds/setundef.cc
View file

@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto &bit : parameter.second.bits) {
for (auto bit : parameter.second) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
@ -390,12 +390,12 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (initval[i] == State::Sx && ffbits.count(bit)) {
initval[i] = worker.next_bit();
initval.bits()[i] = worker.next_bit();
ffbits.erase(bit);
}
}
@ -421,7 +421,7 @@ struct SetundefPass : public Pass {
continue;
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
initval.bits().resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase(ID::init);

2
passes/cmds/splitnets.cc
View file

@ -77,7 +77,7 @@ struct SplitnetsWorker
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
}

12
passes/cmds/xprop.cc
View file

@ -827,9 +827,9 @@ struct XpropWorker
auto init_q_is_1 = init_q;
auto init_q_is_x = init_q;
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = bit == State::Sx ? State::S1 : State::S0;
initvals.remove_init(sig_q);
@ -864,14 +864,14 @@ struct XpropWorker
auto init_q_is_x = init_q;
if (ff.is_anyinit) {
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = State::Sx;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = State::S0;
} else {
for (auto &bit : init_q_is_1)
for (auto &bit : init_q_is_1.bits())
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x)
for (auto &bit : init_q_is_x.bits())
bit = bit == State::Sx ? State::S1 : State::S0;
}