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https://github.com/YosysHQ/yosys
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rtlil: represent Const strings as std::string
This commit is contained in:
Emil J. Tywoniak
parent
61ed9b6263
commit
785bd44da7
90 changed files with 947 additions and 643 deletions
304
kernel/rtlil.cc
304
kernel/rtlil.cc
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@ -202,25 +202,34 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
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return res;
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}
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#define check(condition) log_assert(condition && "malformed Const union")
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Const::bitvectype& Const::get_bits() const {
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check(is_bits());
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return *get_if_bits();
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}
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std::string& Const::get_str() const {
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check(is_str());
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return *get_if_str();
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}
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RTLIL::Const::Const(const std::string &str)
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{
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flags = RTLIL::CONST_FLAG_STRING;
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bits.reserve(str.size() * 8);
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for (int i = str.size()-1; i >= 0; i--) {
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unsigned char ch = str[i];
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for (int j = 0; j < 8; j++) {
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bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
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ch = ch >> 1;
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}
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}
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new ((void*)&str_) std::string(str);
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tag = backing_tag::string;
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}
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RTLIL::Const::Const(long long val, int width)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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bits.reserve(width);
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new ((void*)&bits_) bitvectype();
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tag = backing_tag::bits;
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bitvectype& bv = get_bits();
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bv.reserve(width);
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for (int i = 0; i < width; i++) {
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bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
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bv.push_back((val & 1) != 0 ? State::S1 : State::S0);
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val = val >> 1;
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}
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}
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@ -228,77 +237,167 @@ RTLIL::Const::Const(long long val, int width)
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RTLIL::Const::Const(RTLIL::State bit, int width)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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bits.reserve(width);
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new ((void*)&bits_) bitvectype();
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tag = backing_tag::bits;
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bitvectype& bv = get_bits();
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bv.reserve(width);
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for (int i = 0; i < width; i++)
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bits.push_back(bit);
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bv.push_back(bit);
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}
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RTLIL::Const::Const(const std::vector<bool> &bits)
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{
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flags = RTLIL::CONST_FLAG_NONE;
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this->bits.reserve(bits.size());
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new ((void*)&bits_) bitvectype();
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tag = backing_tag::bits;
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bitvectype& bv = get_bits();
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bv.reserve(bits.size());
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for (const auto &b : bits)
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this->bits.emplace_back(b ? State::S1 : State::S0);
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bv.emplace_back(b ? State::S1 : State::S0);
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}
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bool RTLIL::Const::operator <(const RTLIL::Const &other) const
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RTLIL::Const::Const(const RTLIL::Const &other) {
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tag = other.tag;
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flags = other.flags;
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if (is_str())
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new ((void*)&str_) std::string(other.get_str());
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else if (is_bits())
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new ((void*)&bits_) bitvectype(other.get_bits());
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else
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check(false);
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}
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RTLIL::Const::Const(RTLIL::Const &&other) {
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tag = other.tag;
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flags = other.flags;
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if (is_str())
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new ((void*)&str_) std::string(std::move(other.get_str()));
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else if (is_bits())
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new ((void*)&bits_) bitvectype(std::move(other.get_bits()));
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else
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check(false);
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}
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RTLIL::Const &RTLIL::Const::operator =(const RTLIL::Const &other) {
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flags = other.flags;
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if (other.is_str()) {
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if (!is_str()) {
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// sketchy zone
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check(is_bits());
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bits_.~bitvectype();
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(void)new ((void*)&str_) std::string();
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}
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tag = other.tag;
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get_str() = other.get_str();
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} else if (other.is_bits()) {
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if (!is_bits()) {
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// sketchy zone
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check(is_str());
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str_.~string();
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(void)new ((void*)&bits_) bitvectype();
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}
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tag = other.tag;
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get_bits() = other.get_bits();
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} else {
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check(false);
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}
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return *this;
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}
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RTLIL::Const::~Const() {
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if (is_bits())
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bits_.~bitvectype();
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else if (is_str())
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str_.~string();
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else
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check(false);
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}
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bool RTLIL::Const::operator<(const RTLIL::Const &other) const
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{
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if (bits.size() != other.bits.size())
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return bits.size() < other.bits.size();
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for (size_t i = 0; i < bits.size(); i++)
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if (bits[i] != other.bits[i])
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return bits[i] < other.bits[i];
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if (size() != other.size())
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return size() < other.size();
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for (int i = 0; i < size(); i++)
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if ((*this)[i] != other[i])
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return (*this)[i] < other[i];
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return false;
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}
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bool RTLIL::Const::operator ==(const RTLIL::Const &other) const
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{
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return bits == other.bits;
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if (size() != other.size())
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return false;
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for (int i = 0; i < size(); i++)
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if ((*this)[i] != other[i])
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return false;
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return true;
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}
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bool RTLIL::Const::operator !=(const RTLIL::Const &other) const
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{
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return bits != other.bits;
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return !(*this == other);
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}
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std::vector<RTLIL::State>& RTLIL::Const::bits()
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{
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bitvectorize();
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return get_bits();
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}
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std::vector<RTLIL::State> RTLIL::Const::to_bits() const
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{
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std::vector<State> v;
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for (auto bit : *this)
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v.push_back(bit);
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return v;
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}
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bool RTLIL::Const::as_bool() const
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{
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for (size_t i = 0; i < bits.size(); i++)
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if (bits[i] == State::S1)
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bitvectorize();
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bitvectype& bv = get_bits();
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for (size_t i = 0; i < bv.size(); i++)
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if (bv[i] == State::S1)
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return true;
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return false;
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}
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int RTLIL::Const::as_int(bool is_signed) const
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{
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bitvectorize();
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bitvectype& bv = get_bits();
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int32_t ret = 0;
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for (size_t i = 0; i < bits.size() && i < 32; i++)
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if (bits[i] == State::S1)
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for (size_t i = 0; i < bv.size() && i < 32; i++)
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if (bv[i] == State::S1)
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ret |= 1 << i;
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if (is_signed && bits.back() == State::S1)
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for (size_t i = bits.size(); i < 32; i++)
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if (is_signed && bv.back() == State::S1)
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for (size_t i = bv.size(); i < 32; i++)
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ret |= 1 << i;
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return ret;
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}
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size_t RTLIL::Const::get_min_size(bool is_signed) const
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{
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if (bits.empty()) return 0;
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if (empty()) return 0;
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// back to front (MSB to LSB)
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RTLIL::State leading_bit;
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if (is_signed)
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leading_bit = (bits.back() == RTLIL::State::Sx) ? RTLIL::State::S0 : bits.back();
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leading_bit = (back() == RTLIL::State::Sx) ? RTLIL::State::S0 : back();
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else
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leading_bit = RTLIL::State::S0;
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size_t idx = bits.size();
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while (idx > 0 && bits[idx -1] == leading_bit) {
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size_t idx = size();
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while (idx > 0 && (*this)[idx -1] == leading_bit) {
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idx--;
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}
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// signed needs one leading bit
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if (is_signed && idx < bits.size()) {
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if (is_signed && idx < size()) {
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idx++;
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}
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// must be at least one bit
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@ -308,7 +407,7 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
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void RTLIL::Const::compress(bool is_signed)
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{
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size_t idx = get_min_size(is_signed);
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bits.erase(bits.begin() + idx, bits.end());
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bits().erase(bits().begin() + idx, bits().end());
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}
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std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
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@ -316,28 +415,30 @@ std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
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size_t size = get_min_size(is_signed);
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if(size == 0 || size > 32)
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return std::nullopt;
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int32_t ret = 0;
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for (size_t i = 0; i < size && i < 32; i++)
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if (bits[i] == State::S1)
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if ((*this)[i] == State::S1)
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ret |= 1 << i;
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if (is_signed && bits[size-1] == State::S1)
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if (is_signed && (*this)[size-1] == State::S1)
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for (size_t i = size; i < 32; i++)
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ret |= 1 << i;
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return ret;
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}
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std::string RTLIL::Const::as_string() const
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std::string RTLIL::Const::as_string(const char* any) const
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{
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bitvectorize();
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bitvectype& bv = get_bits();
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std::string ret;
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ret.reserve(bits.size());
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for (size_t i = bits.size(); i > 0; i--)
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switch (bits[i-1]) {
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ret.reserve(bv.size());
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for (size_t i = bv.size(); i > 0; i--)
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switch (bv[i-1]) {
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case S0: ret += "0"; break;
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case S1: ret += "1"; break;
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case Sx: ret += "x"; break;
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case Sz: ret += "z"; break;
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case Sa: ret += "-"; break;
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case Sa: ret += any; break;
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case Sm: ret += "m"; break;
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}
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return ret;
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@ -346,22 +447,28 @@ std::string RTLIL::Const::as_string() const
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RTLIL::Const RTLIL::Const::from_string(const std::string &str)
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{
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Const c;
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c.bits.reserve(str.size());
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bitvectype& bv = c.get_bits();
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bv.reserve(str.size());
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for (auto it = str.rbegin(); it != str.rend(); it++)
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switch (*it) {
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case '0': c.bits.push_back(State::S0); break;
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case '1': c.bits.push_back(State::S1); break;
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case 'x': c.bits.push_back(State::Sx); break;
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case 'z': c.bits.push_back(State::Sz); break;
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case 'm': c.bits.push_back(State::Sm); break;
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default: c.bits.push_back(State::Sa);
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case '0': bv.push_back(State::S0); break;
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case '1': bv.push_back(State::S1); break;
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case 'x': bv.push_back(State::Sx); break;
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case 'z': bv.push_back(State::Sz); break;
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case 'm': bv.push_back(State::Sm); break;
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default: bv.push_back(State::Sa);
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}
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return c;
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}
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std::string RTLIL::Const::decode_string() const
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{
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const int n = GetSize(bits);
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if (auto str = get_if_str())
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return *str;
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bitvectorize();
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bitvectype& bv = get_bits();
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const int n = GetSize(bv);
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const int n_over_8 = n / 8;
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std::string s;
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s.reserve(n_over_8);
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@ -369,7 +476,7 @@ std::string RTLIL::Const::decode_string() const
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if (i < n) {
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char ch = 0;
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for (int j = 0; j < (n - i); j++) {
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if (bits[i + j] == RTLIL::State::S1) {
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if (bv[i + j] == RTLIL::State::S1) {
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ch |= 1 << j;
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}
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}
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@ -380,7 +487,7 @@ std::string RTLIL::Const::decode_string() const
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for (; i >= 0; i -= 8) {
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char ch = 0;
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for (int j = 0; j < 8; j++) {
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if (bits[i + j] == RTLIL::State::S1) {
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if (bv[i + j] == RTLIL::State::S1) {
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ch |= 1 << j;
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}
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}
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@ -390,11 +497,65 @@ std::string RTLIL::Const::decode_string() const
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return s;
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}
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int RTLIL::Const::size() const {
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if (is_str())
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return 8 * str_.size();
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else {
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check(is_bits());
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return bits_.size();
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}
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}
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bool RTLIL::Const::empty() const {
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if (is_str())
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return str_.empty();
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else {
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check(is_bits());
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return bits_.empty();
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}
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}
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void RTLIL::Const::bitvectorize() const {
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if (tag == backing_tag::bits)
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return;
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check(is_str());
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bitvectype new_bits;
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new_bits.reserve(str_.size() * 8);
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for (int i = str_.size() - 1; i >= 0; i--) {
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unsigned char ch = str_[i];
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for (int j = 0; j < 8; j++) {
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new_bits.push_back((ch & 1) != 0 ? State::S1 : State::S0);
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ch = ch >> 1;
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}
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}
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{
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// sketchy zone
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str_.~string();
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(void)new ((void*)&bits_) bitvectype(std::move(new_bits));
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tag = backing_tag::bits;
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}
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}
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RTLIL::State RTLIL::Const::const_iterator::operator*() const {
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if (auto bv = parent.get_if_bits())
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return (*bv)[idx];
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int char_idx = parent.get_str().size() - idx / 8 - 1;
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bool bit = (parent.get_str()[char_idx] & (1 << (idx % 8)));
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return bit ? State::S1 : State::S0;
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}
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bool RTLIL::Const::is_fully_zero() const
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{
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bitvectorize();
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bitvectype& bv = get_bits();
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cover("kernel.rtlil.const.is_fully_zero");
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for (const auto &bit : bits)
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for (const auto &bit : bv)
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if (bit != RTLIL::State::S0)
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return false;
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@ -403,9 +564,11 @@ bool RTLIL::Const::is_fully_zero() const
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bool RTLIL::Const::is_fully_ones() const
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{
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bitvectorize();
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bitvectype& bv = get_bits();
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cover("kernel.rtlil.const.is_fully_ones");
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for (const auto &bit : bits)
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for (const auto &bit : bv)
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if (bit != RTLIL::State::S1)
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return false;
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@ -416,7 +579,10 @@ bool RTLIL::Const::is_fully_def() const
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{
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cover("kernel.rtlil.const.is_fully_def");
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for (const auto &bit : bits)
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bitvectorize();
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bitvectype& bv = get_bits();
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for (const auto &bit : bv)
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if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
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return false;
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@ -427,7 +593,10 @@ bool RTLIL::Const::is_fully_undef() const
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{
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cover("kernel.rtlil.const.is_fully_undef");
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for (const auto &bit : bits)
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bitvectorize();
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bitvectype& bv = get_bits();
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for (const auto &bit : bv)
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if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
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return false;
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@ -438,7 +607,10 @@ bool RTLIL::Const::is_fully_undef_x_only() const
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{
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cover("kernel.rtlil.const.is_fully_undef_x_only");
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for (const auto &bit : bits)
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bitvectorize();
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bitvectype& bv = get_bits();
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for (const auto &bit : bv)
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if (bit != RTLIL::State::Sx)
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return false;
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@ -449,9 +621,12 @@ bool RTLIL::Const::is_onehot(int *pos) const
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{
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cover("kernel.rtlil.const.is_onehot");
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bitvectorize();
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bitvectype& bv = get_bits();
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bool found = false;
|
||||
for (int i = 0; i < GetSize(*this); i++) {
|
||||
auto &bit = bits[i];
|
||||
auto &bit = bv[i];
|
||||
if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
|
||||
return false;
|
||||
if (bit == RTLIL::State::S1) {
|
||||
|
|
@ -465,6 +640,15 @@ bool RTLIL::Const::is_onehot(int *pos) const
|
|||
return found;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::Const::extract(int offset, int len, RTLIL::State padding) const {
|
||||
bitvectype ret_bv;
|
||||
ret_bv.reserve(len);
|
||||
for (int i = offset; i < offset + len; i++)
|
||||
ret_bv.push_back(i < GetSize(*this) ? (*this)[i] : padding);
|
||||
return RTLIL::Const(ret_bv);
|
||||
}
|
||||
#undef check /* check(condition) for Const */
|
||||
|
||||
bool RTLIL::AttrObject::has_attribute(const RTLIL::IdString &id) const
|
||||
{
|
||||
return attributes.count(id);
|
||||
|
|
@ -1112,7 +1296,7 @@ namespace {
|
|||
void param_bits(const RTLIL::IdString& name, int width)
|
||||
{
|
||||
param(name);
|
||||
if (GetSize(cell->parameters.at(name).bits) != width)
|
||||
if (GetSize(cell->parameters.at(name)) != width)
|
||||
error(__LINE__);
|
||||
}
|
||||
|
||||
|
|
@ -3940,7 +4124,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
|
|||
wire = bit.wire;
|
||||
offset = 0;
|
||||
if (wire == NULL)
|
||||
data = RTLIL::Const(bit.data).bits;
|
||||
data = {bit.data};
|
||||
else
|
||||
offset = bit.offset;
|
||||
width = 1;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue