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https://github.com/YosysHQ/yosys
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rtlil: represent Const strings as std::string
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parent
61ed9b6263
commit
785bd44da7
90 changed files with 947 additions and 643 deletions
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@ -325,7 +325,7 @@ struct CellTypes
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static RTLIL::Const eval_not(RTLIL::Const v)
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{
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for (auto &bit : v.bits)
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for (auto &bit : v.bits())
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if (bit == State::S0) bit = State::S1;
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else if (bit == State::S1) bit = State::S0;
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return v;
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@ -419,13 +419,13 @@ struct CellTypes
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RTLIL::Const ret;
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int width = cell->parameters.at(ID::Y_WIDTH).as_int();
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int offset = cell->parameters.at(ID::OFFSET).as_int();
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ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
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ret.bits().insert(ret.bits().end(), arg1.begin()+offset, arg1.begin()+offset+width);
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return ret;
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}
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if (cell->type == ID($concat)) {
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RTLIL::Const ret = arg1;
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ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
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ret.bits().insert(ret.bits().end(), arg2.begin(), arg2.end());
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return ret;
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}
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@ -448,7 +448,7 @@ struct CellTypes
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{
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int width = cell->parameters.at(ID::WIDTH).as_int();
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std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
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std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();
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while (GetSize(t) < (1 << width))
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t.push_back(State::S0);
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t.resize(1 << width);
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@ -460,7 +460,7 @@ struct CellTypes
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{
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int width = cell->parameters.at(ID::WIDTH).as_int();
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int depth = cell->parameters.at(ID::DEPTH).as_int();
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std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
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std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();
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while (GetSize(t) < width*depth*2)
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t.push_back(State::S0);
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@ -473,7 +473,7 @@ struct CellTypes
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bool match_x = true;
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for (int j = 0; j < width; j++) {
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RTLIL::State a = arg1.bits.at(j);
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RTLIL::State a = arg1.at(j);
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if (t.at(2*width*i + 2*j + 0) == State::S1) {
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if (a == State::S1) match_x = false;
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if (a != State::S0) match = false;
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@ -513,7 +513,7 @@ struct CellTypes
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if (cell->type == ID($_OAI3_))
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
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log_assert(arg3.bits.size() == 0);
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log_assert(arg3.size() == 0);
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return eval(cell, arg1, arg2, errp);
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}
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@ -524,7 +524,7 @@ struct CellTypes
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if (cell->type == ID($_OAI4_))
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
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log_assert(arg4.bits.size() == 0);
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log_assert(arg4.size() == 0);
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return eval(cell, arg1, arg2, arg3, errp);
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}
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};
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