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	Merge pull request #3971 from povik/equiv_simple-fixes
Fixes to `equiv_simple`
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						commit
						78541be4d8
					
				
					 1 changed files with 4 additions and 4 deletions
				
			
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			@ -60,7 +60,7 @@ struct EquivSimpleWorker
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		for (auto &conn : cell->connections())
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			if (yosys_celltypes.cell_input(cell->type, conn.first))
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				for (auto bit : sigmap(conn.second)) {
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					if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
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					if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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						if (!conn.first.in(ID::CLK, ID::C))
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							next_seed.insert(bit);
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					} else
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			@ -133,11 +133,9 @@ struct EquivSimpleWorker
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			for (auto bit_a : seed_a)
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				find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a);
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			next_seed_a.clear();
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			for (auto bit_b : seed_b)
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				find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b);
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			next_seed_b.clear();
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			pool<Cell*> short_cells_cone_a, short_cells_cone_b;
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			pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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			@ -145,10 +143,12 @@ struct EquivSimpleWorker
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			if (short_cones)
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			{
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				next_seed_a.clear();
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				for (auto bit_a : seed_a)
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					find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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				next_seed_a.swap(seed_a);
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				next_seed_b.clear();
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				for (auto bit_b : seed_b)
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					find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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				next_seed_b.swap(seed_b);
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			@ -364,7 +364,7 @@ struct EquivSimplePass : public Pass {
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					unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
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			for (auto cell : module->cells()) {
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				if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
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				if (!ct.cell_known(cell->type))
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					continue;
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				for (auto &conn : cell->connections())
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					if (yosys_celltypes.cell_output(cell->type, conn.first))
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