From 780f1bd7057867d324320229426576a2a284eaf1 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 9 Jul 2026 17:22:05 -0700 Subject: [PATCH] Smallfixes --- passes/opt/opt_first_fit_alloc.cc | 16 +++++++ passes/silimate/opt_vps.cc | 70 ++++++++++++------------------- 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/passes/opt/opt_first_fit_alloc.cc b/passes/opt/opt_first_fit_alloc.cc index caf1e3888..935bfdd1e 100644 --- a/passes/opt/opt_first_fit_alloc.cc +++ b/passes/opt/opt_first_fit_alloc.cc @@ -594,6 +594,14 @@ struct OptFirstFitAllocWorker : CutRegionWorker { } SigBit emit_and(Cell *anchor, SigBit a, SigBit b) { + // Const-fold 0/1 operands so prefix-OR / category scans don't emit + // dead $and cells that only inflate cells_added until opt_expr. + if (a == State::S0 || b == State::S0) + return State::S0; + if (a == State::S1) + return b; + if (b == State::S1) + return a; Cell *cell = anchor; SigBit o = module->And(NEW_ID2_SUFFIX("ffa_and"), SigSpec(a), SigSpec(b), false, cell_src(anchor))[0]; cells_added++; @@ -601,6 +609,14 @@ struct OptFirstFitAllocWorker : CutRegionWorker { } SigBit emit_or(Cell *anchor, SigBit a, SigBit b) { + // Same for $or: exclusive prefix starts at S0 and would otherwise + // produce a cascade of (x | 0) cells on every Hillis-Steele step. + if (a == State::S1 || b == State::S1) + return State::S1; + if (a == State::S0) + return b; + if (b == State::S0) + return a; Cell *cell = anchor; SigBit o = module->Or(NEW_ID2_SUFFIX("ffa_or"), SigSpec(a), SigSpec(b), false, cell_src(anchor))[0]; cells_added++; diff --git a/passes/silimate/opt_vps.cc b/passes/silimate/opt_vps.cc index 360e11b55..662e040a5 100644 --- a/passes/silimate/opt_vps.cc +++ b/passes/silimate/opt_vps.cc @@ -23,6 +23,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +#include "passes/opt/rewrite_utils.h" + struct OptVpsWorker { struct PmuxInfo { @@ -476,12 +478,10 @@ struct OptVpsWorker Wire *sub_w = module->addWire( NEW_ID_SUFFIX("vps_merge_idx"), GetSize(binary_index)); - Cell *sub = module->addSub(NEW_ID_SUFFIX("vps_merge_sub"), + module->addSub(NEW_ID_SUFFIX("vps_merge_sub"), binary_index, Const(base_sub, GetSize(binary_index)), - sub_w); - sub->add_strpool_attribute(ID::src, - lowest.pmux->get_strpool_attribute(ID::src)); + sub_w, false, cell_src(lowest.pmux)); raw_idx = SigSpec(sub_w); } else { raw_idx = binary_index; @@ -557,9 +557,7 @@ struct OptVpsWorker Wire *merged_y = module->addWire( NEW_ID_SUFFIX("vps_merge_y"), combined_W); Cell *shr = module->addShr(NEW_ID_SUFFIX("vps_merge_shr"), - source, shift_amount, SigSpec(merged_y)); - shr->add_strpool_attribute(ID::src, - lowest.pmux->get_strpool_attribute(ID::src)); + source, shift_amount, SigSpec(merged_y), false, cell_src(lowest.pmux)); vps_shr_cells.insert(shr); int lowest_eff_off = eff_offset(lowest); @@ -678,12 +676,10 @@ struct OptVpsWorker Wire *sub_w = module->addWire( NEW_ID_SUFFIX("vps_merge_idx"), GetSize(binary_index)); - Cell *sub = module->addSub(NEW_ID_SUFFIX("vps_merge_sub"), + module->addSub(NEW_ID_SUFFIX("vps_merge_sub"), binary_index, Const(lowest_base, GetSize(binary_index)), - sub_w); - sub->add_strpool_attribute(ID::src, - lowest.pmux->get_strpool_attribute(ID::src)); + sub_w, false, cell_src(lowest.pmux)); raw_idx = SigSpec(sub_w); } @@ -752,9 +748,7 @@ struct OptVpsWorker Wire *merged_y = module->addWire( NEW_ID_SUFFIX("vps_merge_y"), combined_W); Cell *shr = module->addShr(NEW_ID_SUFFIX("vps_merge_shr"), - source, shift_amount, SigSpec(merged_y)); - shr->add_strpool_attribute(ID::src, - ref_pmux->get_strpool_attribute(ID::src)); + source, shift_amount, SigSpec(merged_y), false, cell_src(ref_pmux)); vps_shr_cells.insert(shr); int lowest_eff_off = eff_offset(lowest); @@ -935,9 +929,7 @@ struct OptVpsWorker NEW_ID_SUFFIX("vps_shared_y"), reg_width); Cell *shared_shr = module->addShr( NEW_ID_SUFFIX("vps_shared_shr"), - reg_source, ref_shift, SigSpec(shared_y)); - shared_shr->add_strpool_attribute(ID::src, - ref_info.shr->get_strpool_attribute(ID::src)); + reg_source, ref_shift, SigSpec(shared_y), false, cell_src(ref_info.shr)); log(" VPS shared barrel shifter: %s (reg=%s, width=%d, " "align=%d, serves %d reads, ref_offset=%d)\n", @@ -1194,9 +1186,9 @@ struct OptVpsWorker SigSpec raw_idx = binary_index; if (base > 0) { Wire *sub_w = module->addWire(NEW_ID_SUFFIX("vps_rd_idx"), GetSize(binary_index)); - Cell *sub = module->addSub(NEW_ID_SUFFIX("vps_rd_sub"), - binary_index, Const(base, GetSize(binary_index)), sub_w); - sub->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + module->addSub(NEW_ID_SUFFIX("vps_rd_sub"), + binary_index, Const(base, GetSize(binary_index)), sub_w, + false, cell_src(cell)); raw_idx = SigSpec(sub_w); } if (log2_align > 0) { @@ -1212,8 +1204,7 @@ struct OptVpsWorker src_bits = GetSize(source); Cell *shr = module->addShr(NEW_ID_SUFFIX("vps_rd_shr"), - source, shift_amount, sig_y); - shr->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + source, shift_amount, sig_y, false, cell_src(cell)); vps_shr_cells.insert(shr); } else { // Stride=W: pack windows sequentially, shift by W*binary_index @@ -1264,8 +1255,7 @@ struct OptVpsWorker src_bits = GetSize(packed); Cell *shr = module->addShr(NEW_ID_SUFFIX("vps_rd_shr"), - packed, shifted_idx, sig_y); - shr->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + packed, shifted_idx, sig_y, false, cell_src(cell)); vps_shr_cells.insert(shr); } @@ -1466,10 +1456,9 @@ struct OptVpsWorker if (upper_width > 0) { int lane_idx = base / W + L; Wire *eq_w = module->addWire(NEW_ID_SUFFIX("vps_lane_eq"), 1); - Cell *eq = module->addEq(NEW_ID_SUFFIX("vps_lane_cmp"), - upper_bits, Const(lane_idx, upper_width), eq_w); - eq->add_strpool_attribute(ID::src, - candidates[group_start + L * W].cell->get_strpool_attribute(ID::src)); + module->addEq(NEW_ID_SUFFIX("vps_lane_cmp"), + upper_bits, Const(lane_idx, upper_width), eq_w, + false, cell_src(candidates[group_start + L * W].cell)); range_bit = SigBit(eq_w); } else { range_bit = State::S1; @@ -1495,9 +1484,8 @@ struct OptVpsWorker lane_en[L] = lane_bits[0]; } else { Wire *w = module->addWire(NEW_ID_SUFFIX("vps_lane_en"), 1); - Cell *ror = module->addReduceOr(NEW_ID_SUFFIX("vps_lane_or"), lane_bits, w); - ror->add_strpool_attribute(ID::src, - candidates[group_start + L * W].cell->get_strpool_attribute(ID::src)); + module->addReduceOr(NEW_ID_SUFFIX("vps_lane_or"), lane_bits, w, + false, cell_src(candidates[group_start + L * W].cell)); lane_en[L] = SigBit(w); } } @@ -1609,17 +1597,14 @@ struct OptVpsWorker } Wire *gated_w = module->addWire(NEW_ID_SUFFIX("vps_wr_lane_en"), 1); - Cell *lane_and = module->addAnd(NEW_ID_SUFFIX("vps_wr_lane_and"), + Cell *src_cell = candidates[group_start + L * W].cell; + module->addAnd(NEW_ID_SUFFIX("vps_wr_lane_and"), SigSpec(wr_en_sig), SigSpec(lane_en[L]), - SigSpec(gated_w)); - lane_and->add_strpool_attribute(ID::src, - candidates[group_start + L * W].cell->get_strpool_attribute(ID::src)); + SigSpec(gated_w), false, cell_src(src_cell)); - Cell *lane_mux = module->addMux( + module->addMux( NEW_ID_SUFFIX("vps_lane_mux"), - q_lane, data_lane, SigBit(gated_w), fb_y_lane); - lane_mux->add_strpool_attribute(ID::src, - candidates[group_start + L * W].cell->get_strpool_attribute(ID::src)); + q_lane, data_lane, SigBit(gated_w), fb_y_lane, cell_src(src_cell)); } for (auto c : cells_to_remove) @@ -1648,10 +1633,9 @@ struct OptVpsWorker SigBit data_bit = cell_b[W - 1 - b]; SigSpec sig_y = pmux_cell->getPort(ID::Y); - Cell *mux = module->addMux(NEW_ID_SUFFIX("vps_mux"), - State::S0, data_bit, lane_en[L], sig_y); - mux->add_strpool_attribute(ID::src, - pmux_cell->get_strpool_attribute(ID::src)); + module->addMux(NEW_ID_SUFFIX("vps_mux"), + State::S0, data_bit, lane_en[L], sig_y, + cell_src(pmux_cell)); SigSpec pmux_s = sigmap(pmux_cell->getPort(ID::S)); auto it = reduce_or_map.find(pmux_s);