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ast: Move to a new helper method to print input errors
It's a repeating pattern to print an error message tied to an AST node. Start using an 'input_error' helper for that. Among other things this is beneficial in shortening the print lines, which tend to be long.
This commit is contained in:
Martin Povišer
Zachary Snow
parent
1ac1b2eed5
commit
77d4b5230e
6 changed files with 204 additions and 195 deletions
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@ -56,7 +56,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
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if (gen_attributes)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -88,7 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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if (that != NULL)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -114,7 +114,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -149,7 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -325,8 +325,7 @@ struct AST_INTERNAL::ProcessGenerator
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set_src_attr(proc, always);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
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attr.first.c_str());
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always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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proc->attributes[attr.first] = attr.second->asAttrConst();
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}
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current_case = &proc->root_case;
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@ -355,7 +354,7 @@ struct AST_INTERNAL::ProcessGenerator
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if (found_anyedge_syncs) {
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if (found_global_syncs)
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log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
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always->input_error("Found non-synthesizable event list!\n");
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log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str());
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log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
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log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
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@ -370,12 +369,12 @@ struct AST_INTERNAL::ProcessGenerator
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continue;
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found_clocked_sync = true;
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if (found_global_syncs || found_anyedge_syncs)
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log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
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always->input_error("Found non-synthesizable event list!\n");
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RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
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syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
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syncrule->signal = child->children[0]->genRTLIL();
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if (GetSize(syncrule->signal) != 1)
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log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
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always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n");
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addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
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proc->syncs.push_back(syncrule);
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}
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@ -604,7 +603,7 @@ struct AST_INTERNAL::ProcessGenerator
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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sw->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -682,16 +681,16 @@ struct AST_INTERNAL::ProcessGenerator
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break;
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case AST_WIRE:
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log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n");
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ast->input_error("Found reg declaration in block without label!\n");
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break;
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case AST_ASSIGN:
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log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n");
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ast->input_error("Found continous assignment in always/initial block!\n");
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break;
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case AST_PARAMETER:
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case AST_LOCALPARAM:
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log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n");
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ast->input_error("Found parameter declaration in block without label!\n");
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break;
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case AST_NONE:
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@ -840,7 +839,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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}
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}
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if (!id_ast)
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log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
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input_error("Failed to resolve identifier %s for width detection!\n", str.c_str());
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if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
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if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
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this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
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@ -850,7 +849,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (id_ast->children[0]->type == AST_CONSTANT)
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this_width = id_ast->children[0]->bits.size();
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else
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log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str());
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input_error("Failed to detect width for parameter %s!\n", str.c_str());
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}
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if (children.size() != 0)
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range = children[0];
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@ -863,7 +862,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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// log("---\n");
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// id_ast->dumpAst(NULL, "decl> ");
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// dumpAst(NULL, "ref> ");
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log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str());
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input_error("Failed to detect width of signal access `%s'!\n", str.c_str());
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}
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} else {
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this_width = id_ast->range_left - id_ast->range_right + 1;
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@ -874,7 +873,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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this_width = 32;
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} else if (id_ast->type == AST_MEMORY) {
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if (!id_ast->children[0]->range_valid)
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log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
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input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
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this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
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if (children.size() > 1)
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range = children[1];
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@ -883,7 +882,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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this_width = tmp_range->range_left - tmp_range->range_right + 1;
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delete tmp_range;
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} else
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log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());
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input_error("Failed to detect width for identifier %s!\n", str.c_str());
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if (range) {
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if (range->children.size() == 1)
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this_width = 1;
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@ -893,7 +892,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
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input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
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this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
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delete left_at_zero_ast;
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delete right_at_zero_ast;
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@ -909,7 +908,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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case AST_TO_BITS:
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while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n");
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input_error("Left operand of tobits expression is not constant!\n");
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children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
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width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
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break;
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@ -931,12 +930,12 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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case AST_CAST_SIZE:
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while (children.at(0)->simplify(true, false, false, 1, -1, false, false)) { }
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if (children.at(0)->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
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input_error("Static cast with non constant expression!\n");
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children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
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this_width = children.at(0)->bitsAsConst().as_int();
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width_hint = max(width_hint, this_width);
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if (width_hint <= 0)
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log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
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input_error("Static cast with zero or negative size!\n");
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break;
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case AST_CONCAT:
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@ -953,7 +952,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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case AST_REPLICATE:
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while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
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input_error("Left operand of replicate expression is not constant!\n");
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children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
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width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
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sign_hint = false;
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@ -1029,7 +1028,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (!id2ast->is_signed)
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sign_hint = false;
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if (!id2ast->children[0]->range_valid)
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log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
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input_error("Failed to detect width of memory access `%s'!\n", str.c_str());
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this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
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width_hint = max(width_hint, this_width);
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break;
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@ -1073,7 +1072,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (GetSize(children) == 1) {
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while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
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input_error("System function %s called with non-const argument!\n",
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RTLIL::unescape_id(str).c_str());
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width_hint = max(width_hint, int(children[0]->asInt(true)));
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}
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@ -1101,7 +1100,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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// item expressions.
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const AstNode *func = current_scope.at(str);
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if (func->type != AST_FUNCTION)
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log_file_error(filename, location.first_line, "Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str());
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input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str());
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const AstNode *wire = nullptr;
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for (const AstNode *child : func->children)
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if (child->str == func->str) {
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@ -1121,7 +1120,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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while (left->simplify(true, false, false, 1, -1, false, true)) { }
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while (right->simplify(true, false, false, 1, -1, false, true)) { }
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if (left->type != AST_CONSTANT || right->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Function %s has non-constant width!",
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input_error("Function %s has non-constant width!",
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RTLIL::unescape_id(str).c_str());
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result_width = abs(int(left->asInt(true) - right->asInt(true)));
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delete left;
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@ -1137,7 +1136,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod;
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for (auto f : log_files)
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current_scope_ast->dumpAst(f, "verilog-ast> ");
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log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
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input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
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}
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if (*found_real)
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@ -1155,9 +1154,8 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
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constexpr int kWidthLimit = 1 << 24;
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if (width_hint >= kWidthLimit)
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log_file_error(filename, location.first_line,
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"Expression width %d exceeds implementation limit of %d!\n",
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width_hint, kWidthLimit);
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input_error("Expression width %d exceeds implementation limit of %d!\n",
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width_hint, kWidthLimit);
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}
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static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
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@ -1168,9 +1166,8 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
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std::string location_str = "earlier";
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if (!src.empty())
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location_str = "at " + src;
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log_file_error(node->filename, node->location.first_line,
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"Cannot add %s `%s' because a %s with the same name was already created %s!\n",
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to_add_kind, id.c_str(), existing_kind, location_str.c_str());
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node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n",
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to_add_kind, id.c_str(), existing_kind, location_str.c_str());
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};
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if (const RTLIL::Wire *wire = module->wire(id))
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@ -1265,7 +1262,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (flag_pwires)
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{
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if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str());
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input_error("Parameter `%s' with non-constant value!\n", str.c_str());
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RTLIL::Const val = children[0]->bitsAsConst();
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RTLIL::IdString id = str;
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@ -1279,7 +1276,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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wire->attributes[attr.first] = attr.second->asAttrConst();
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}
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}
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@ -1288,10 +1285,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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// create an RTLIL::Wire for an AST_WIRE node
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case AST_WIRE: {
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if (!range_valid)
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log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
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input_error("Signal `%s' with non-constant width!\n", str.c_str());
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if (!(range_left + 1 >= range_right))
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log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
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input_error("Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
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RTLIL::IdString id = str;
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check_unique_id(current_module, id, this, "signal");
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@ -1306,7 +1303,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
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wire->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -1322,7 +1319,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_assert(children[1]->type == AST_RANGE);
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if (!children[0]->range_valid || !children[1]->range_valid)
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log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
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input_error("Memory `%s' with non-constant width or size!\n", str.c_str());
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RTLIL::Memory *memory = new RTLIL::Memory;
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set_src_attr(memory, this);
|
||||
|
|
@ -1340,7 +1337,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
memory->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
}
|
||||
|
|
@ -1397,11 +1394,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
} else if (flag_autowire)
|
||||
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
else
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
||||
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
||||
}
|
||||
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
|
||||
if (id2ast->children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str());
|
||||
input_error("Parameter %s does not evaluate to constant value!\n", str.c_str());
|
||||
chunk = RTLIL::Const(id2ast->children[0]->bits);
|
||||
goto use_const_chunk;
|
||||
}
|
||||
|
|
@ -1416,11 +1413,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
is_interface = true;
|
||||
}
|
||||
else {
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
|
||||
input_error("Identifier `%s' doesn't map to any signal!\n", str.c_str());
|
||||
}
|
||||
|
||||
if (id2ast->type == AST_MEMORY)
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
|
||||
input_error("Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
|
||||
|
||||
// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
|
||||
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
|
||||
|
|
@ -1449,7 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
use_const_chunk:
|
||||
if (children.size() != 0) {
|
||||
if (children[0]->type != AST_RANGE)
|
||||
log_file_error(filename, location.first_line, "Single range expected.\n");
|
||||
input_error("Single range expected.\n");
|
||||
int source_width = id2ast->range_left - id2ast->range_right + 1;
|
||||
int source_offset = id2ast->range_right;
|
||||
int chunk_left = source_width - 1;
|
||||
|
|
@ -1468,7 +1465,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
|
||||
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
|
||||
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
||||
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
children[0]->children[1]->clone() : children[0]->children[0]->clone());
|
||||
|
|
@ -1553,10 +1550,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
case AST_CAST_SIZE: {
|
||||
RTLIL::SigSpec size = children[0]->genRTLIL();
|
||||
if (!size.is_fully_const())
|
||||
log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
|
||||
input_error("Static cast with non constant expression!\n");
|
||||
int width = size.as_int();
|
||||
if (width <= 0)
|
||||
log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
|
||||
input_error("Static cast with zero or negative size!\n");
|
||||
// determine the *signedness* of the expression
|
||||
int sub_width_hint = -1;
|
||||
bool sub_sign_hint = true;
|
||||
|
|
@ -1585,7 +1582,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
RTLIL::SigSpec left = children[0]->genRTLIL();
|
||||
RTLIL::SigSpec right = children[1]->genRTLIL();
|
||||
if (!left.is_fully_const())
|
||||
log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
|
||||
input_error("Left operand of replicate expression is not constant!\n");
|
||||
int count = left.as_int();
|
||||
RTLIL::SigSpec sig;
|
||||
for (int i = 0; i < count; i++)
|
||||
|
|
@ -1845,7 +1842,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
id2ast->meminfo(mem_width, mem_size, addr_bits);
|
||||
|
||||
if (children[3]->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
|
||||
input_error("Memory init with non-constant word count!\n");
|
||||
int num_words = int(children[3]->asInt(false));
|
||||
cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
|
||||
|
||||
|
|
@ -1899,7 +1896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
|
||||
|
|
@ -1958,7 +1955,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_id(cell), log_id(paraname), value->realvalue);
|
||||
else if (value->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",
|
||||
input_error("Parameter %s.%s with non-constant value!\n",
|
||||
log_id(cell), log_id(paraname));
|
||||
cell->parameters[paraname] = value->asParaConst();
|
||||
continue;
|
||||
|
|
@ -2006,7 +2003,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
|
||||
input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str());
|
||||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
if (cell->type == ID($specify2)) {
|
||||
|
|
@ -2014,7 +2011,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int dst_width = GetSize(cell->getPort(ID::DST));
|
||||
bool full = cell->getParam(ID::FULL).as_bool();
|
||||
if (!full && src_width != dst_width)
|
||||
log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
|
||||
input_error("Parallel specify SRC width does not match DST width.\n");
|
||||
cell->setParam(ID::SRC_WIDTH, Const(src_width));
|
||||
cell->setParam(ID::DST_WIDTH, Const(dst_width));
|
||||
}
|
||||
|
|
@ -2022,7 +2019,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int dat_width = GetSize(cell->getPort(ID::DAT));
|
||||
int dst_width = GetSize(cell->getPort(ID::DST));
|
||||
if (dat_width != dst_width)
|
||||
log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
|
||||
input_error("Specify DAT width does not match DST width.\n");
|
||||
int src_width = GetSize(cell->getPort(ID::SRC));
|
||||
cell->setParam(ID::SRC_WIDTH, Const(src_width));
|
||||
cell->setParam(ID::DST_WIDTH, Const(dst_width));
|
||||
|
|
@ -2064,20 +2061,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
log_file_warning(filename, location.first_line, "\n");
|
||||
} else if (str == "$error") {
|
||||
if (sz > 0)
|
||||
log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
input_error("%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_error(filename, location.first_line, "\n");
|
||||
input_error("\n");
|
||||
} else if (str == "$fatal") {
|
||||
// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
|
||||
// if no parameter is given, default value is 1
|
||||
// dollar_finish(sz ? children[0] : 1);
|
||||
// perhaps create & use log_file_fatal()
|
||||
if (sz > 0)
|
||||
log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str());
|
||||
input_error("FATAL: %s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_error(filename, location.first_line, "FATAL.\n");
|
||||
input_error("FATAL.\n");
|
||||
} else {
|
||||
log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str());
|
||||
input_error("Unknown elabortoon system task '%s'.\n", str.c_str());
|
||||
}
|
||||
} break;
|
||||
|
||||
|
|
@ -2095,18 +2092,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int width = width_hint;
|
||||
|
||||
if (GetSize(children) > 1)
|
||||
log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n",
|
||||
input_error("System function %s got %d arguments, expected 1 or 0.\n",
|
||||
RTLIL::unescape_id(str).c_str(), GetSize(children));
|
||||
|
||||
if (GetSize(children) == 1) {
|
||||
if (children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
|
||||
input_error("System function %s called with non-const argument!\n",
|
||||
RTLIL::unescape_id(str).c_str());
|
||||
width = children[0]->asInt(true);
|
||||
}
|
||||
|
||||
if (width <= 0)
|
||||
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
|
||||
Cell *cell = current_module->addCell(myid, str.substr(1));
|
||||
set_src_attr(cell, this);
|
||||
|
|
@ -2115,7 +2112,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (attributes.count(ID::reg)) {
|
||||
auto &attr = attributes.at(ID::reg);
|
||||
if (attr->type != AST_CONSTANT)
|
||||
log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
|
||||
input_error("Attribute `reg' with non-constant value!\n");
|
||||
cell->attributes[ID::reg] = attr->asAttrConst();
|
||||
}
|
||||
|
||||
|
|
@ -2133,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
default:
|
||||
for (auto f : log_files)
|
||||
current_ast_mod->dumpAst(f, "verilog-ast> ");
|
||||
log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str());
|
||||
input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str());
|
||||
}
|
||||
|
||||
return RTLIL::SigSpec();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue