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Add Verilog "automatic" keyword (ignored in synthesis)

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This commit is contained in:
Clifford Wolf 2017-11-23 08:48:17 +01:00
parent 5b6e52118c
commit 777f2881d8
2 changed files with 18 additions and 13 deletions
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frontends/verilog/verilog_lexer.l
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@ -170,6 +170,7 @@ YOSYS_NAMESPACE_END
"endgenerate" { return TOK_ENDGENERATE; }
"while" { return TOK_WHILE; }
"repeat" { return TOK_REPEAT; }
"automatic" { return TOK_AUTOMATIC; }
"unique" { SV_KEYWORD(TOK_UNIQUE); }
"unique0" { SV_KEYWORD(TOK_UNIQUE); }