initial import

tests/or1200/config.patch

@@ -0,0 +1,46 @@
+Index: or1200_defines.v
+===================================================================
+--- or1200_defines.v	(revision 812)
++++ or1200_defines.v	(working copy)
+@@ -56,7 +56,7 @@
+ //
+ //`define OR1200_VERBOSE
+ 
+-//  `define OR1200_ASIC
++`define OR1200_ASIC
+ ////////////////////////////////////////////////////////
+ //
+ // Typical configuration for an ASIC
+@@ -69,7 +69,7 @@
+ //`define OR1200_ARTISAN_SSP
+ //`define OR1200_ARTISAN_SDP
+ //`define OR1200_ARTISAN_STP
+-`define OR1200_VIRTUALSILICON_SSP
++//`define OR1200_VIRTUALSILICON_SSP
+ //`define OR1200_VIRTUALSILICON_STP_T1
+ //`define OR1200_VIRTUALSILICON_STP_T2
+ 
+@@ -96,17 +96,17 @@
+ //
+ // Select between ASIC optimized and generic multiplier
+ //
+-//`define OR1200_ASIC_MULTP2_32X32
+-`define OR1200_GENERIC_MULTP2_32X32
++`define OR1200_ASIC_MULTP2_32X32
++//`define OR1200_GENERIC_MULTP2_32X32
+ 
+ //
+ // Size/type of insn/data cache if implemented
+ //
+-// `define OR1200_IC_1W_512B
++`define OR1200_IC_1W_512B
+ // `define OR1200_IC_1W_4KB
+-`define OR1200_IC_1W_8KB
+-// `define OR1200_DC_1W_4KB
+-`define OR1200_DC_1W_8KB
++// `define OR1200_IC_1W_8KB
++`define OR1200_DC_1W_4KB
++// `define OR1200_DC_1W_8KB
+ 
+ `else
+ 

tests/or1200/run-checkout.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+rm -rf rtl
+svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200/rtl/verilog rtl
+( cd rtl; patch -p0 < ../config.patch; )

tests/or1200/run-fm-mods.sh

@@ -0,0 +1,24 @@
+#!/bin/bash
+if [ -n "$REMOTE_YOSYS_ROOT" ]; then
+	rsync --exclude=".svn" --exclude="*.log" -rv -e "${REMOTE_YOSYS_SSH:-ssh} -C" "$REMOTE_YOSYS_ROOT"/tests/or1200/. .
+fi
+for mod in $( grep '^module or1200_' synth.v | awk -F '[ (]' '{ print $2; }'; )
+do
+	{
+		grep '^set ' run-fm.do
+		grep '^read_verilog -container r ' run-fm.do
+		echo "set_top r:/WORK/$mod"
+		grep '^read_verilog -container i ' run-fm.do
+		echo "set_top i:/WORK/$mod"
+		echo "verify"
+		echo "exit"
+	} > run-fm-${mod}.do
+	fm_shell -64 -file run-fm-${mod}.do 2>&1 | tee run-fm-${mod}.log
+	rsync -v -e "${REMOTE_YOSYS_SSH:-ssh}" run-fm-${mod}.log "$REMOTE_YOSYS_ROOT"/tests/or1200/
+done
+
+echo; echo
+for x in run-fm-*.log; do
+	echo -e "${x%/*}\\t$( egrep '^Verification (SUCCEEDED|FAILED)' $x; )"
+done | expand -t20
+echo; echo

tests/or1200/run-fm.do

@@ -0,0 +1,53 @@
+
+set hdlin_ignore_full_case false
+set hdlin_warn_on_mismatch_message "FMR_ELAB-115 FMR_VLOG-079 FMR_VLOG-091"
+
+read_verilog -container r -libname WORK -01 rtl/or1200_alu.v
+read_verilog -container r -libname WORK -01 rtl/or1200_amultp2_32x32.v
+read_verilog -container r -libname WORK -01 rtl/or1200_cfgr.v
+read_verilog -container r -libname WORK -01 rtl/or1200_cpu.v
+read_verilog -container r -libname WORK -01 rtl/or1200_ctrl.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dc_fsm.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dc_ram.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dc_tag.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dc_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dmmu_tlb.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dmmu_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_dpram.v
+read_verilog -container r -libname WORK -01 rtl/or1200_du.v
+read_verilog -container r -libname WORK -01 rtl/or1200_except.v
+read_verilog -container r -libname WORK -01 rtl/or1200_fpu.v
+read_verilog -container r -libname WORK -01 rtl/or1200_freeze.v
+read_verilog -container r -libname WORK -01 rtl/or1200_genpc.v
+read_verilog -container r -libname WORK -01 rtl/or1200_ic_fsm.v
+read_verilog -container r -libname WORK -01 rtl/or1200_ic_ram.v
+read_verilog -container r -libname WORK -01 rtl/or1200_ic_tag.v
+read_verilog -container r -libname WORK -01 rtl/or1200_ic_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_if.v
+read_verilog -container r -libname WORK -01 rtl/or1200_immu_tlb.v
+read_verilog -container r -libname WORK -01 rtl/or1200_immu_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_lsu.v
+read_verilog -container r -libname WORK -01 rtl/or1200_mem2reg.v
+read_verilog -container r -libname WORK -01 rtl/or1200_mult_mac.v
+read_verilog -container r -libname WORK -01 rtl/or1200_operandmuxes.v
+read_verilog -container r -libname WORK -01 rtl/or1200_pic.v
+read_verilog -container r -libname WORK -01 rtl/or1200_pm.v
+read_verilog -container r -libname WORK -01 rtl/or1200_qmem_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_reg2mem.v
+read_verilog -container r -libname WORK -01 rtl/or1200_rf.v
+read_verilog -container r -libname WORK -01 rtl/or1200_sb.v
+read_verilog -container r -libname WORK -01 rtl/or1200_spram_32_bw.v
+read_verilog -container r -libname WORK -01 rtl/or1200_spram.v
+read_verilog -container r -libname WORK -01 rtl/or1200_sprs.v
+read_verilog -container r -libname WORK -01 rtl/or1200_top.v
+read_verilog -container r -libname WORK -01 rtl/or1200_tt.v
+read_verilog -container r -libname WORK -01 rtl/or1200_wb_biu.v
+read_verilog -container r -libname WORK -01 rtl/or1200_wbmux.v
+set_top r:/WORK/or1200_top
+
+read_verilog -container i -libname WORK -01 synth.v
+read_verilog -container i -technology_library -libname TECH_WORK -01 ../../techlibs/stdcells_sim.v
+set_top i:/WORK/or1200_top
+
+if ![verify] start_gui exit
+

tests/or1200/run-fm.sh

@@ -0,0 +1,5 @@
+#!/bin/bash
+if [ -n "$REMOTE_YOSYS_ROOT" ]; then
+	rsync --exclude=".svn" --exclude="*.log" -rv -e "${REMOTE_YOSYS_SSH:-ssh} -C" "$REMOTE_YOSYS_ROOT"/tests/or1200/. .
+fi
+fm_shell -64 -file run-fm.do 2>&1 | tee run-fm.log

tests/or1200/run-synth.sh

@@ -0,0 +1,2 @@
+#!/bin/bash
+time ../../yosys -b "verilog -noexpr" -o synth.v -tl synth.log -s run-synth.ys rtl/or1200_*.v 2>&1 | egrep '^\[[0-9.]+\] (ERROR|--|[0-9]+\.)'

tests/or1200/run-synth.ys

@@ -0,0 +1,11 @@
+hierarchy -check -top or1200_top
+proc
+opt
+memory
+opt
+# fsm -norecode
+# opt
+techmap
+opt
+abc
+opt

tests/or1200/run-vg.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+time valgrind --leak-check=full --show-reachable=yes --log-file=valgrind.log \
+		../../yosys -o synth.v -tl synth.log -p "hierarchy -check -top or1200_top" \
+		-p opt_const -p proc -p memory -p opt -p techmap -p opt -p abc -p opt rtl/or1200_*.v