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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/no-icarus/autowire.v Normal file
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module test01(a, b, y);
input [3:0] a, b;
output [3:0] y;
assign temp1 = a + b;
assign temp2 = ~temp1;
assign y = temp2;
endmodule
// ------------------------------
module test02(a, b, y);
input [3:0] a, b;
output [3:0] y;
test01 test01_cell(A, B, Y);
assign A = a, B = b, y = Y;
endmodule