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This commit is contained in:
Clifford Wolf
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134
tests/iwls2005/simple_spi/fifo4.v
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134
tests/iwls2005/simple_spi/fifo4.v
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// FIFO 4 entries deep ////
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//// ////
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//// Authors: Rudolf Usselmann, Richard Herveille ////
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//// rudi@asics.ws richard@asics.ws ////
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//// ////
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//// ////
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//// Download from: http://www.opencores.org/projects/sasc ////
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//// http://www.opencores.org/projects/simple_spi ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
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//// www.asics.ws ////
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//// rudi@asics.ws, richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: fifo4.v,v 1.1.1.1 2002/12/22 16:07:14 rherveille Exp $
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//
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// $Date: 2002/12/22 16:07:14 $
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// $Revision: 1.1.1.1 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: fifo4.v,v $
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// Revision 1.1.1.1 2002/12/22 16:07:14 rherveille
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// Initial release
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// 4 entry deep fast fifo
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module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
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parameter dw = 8;
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input clk, rst;
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input clr;
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input [dw:1] din;
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input we;
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output [dw:1] dout;
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input re;
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output full, empty;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg [dw:1] mem[0:3];
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reg [1:0] wp;
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reg [1:0] rp;
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wire [1:0] wp_p1;
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wire [1:0] wp_p2;
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wire [1:0] rp_p1;
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wire full, empty;
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reg gb;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(posedge clk or negedge rst)
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if(!rst) wp <= #1 2'h0;
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else
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if(clr) wp <= #1 2'h0;
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else
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if(we) wp <= #1 wp_p1;
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assign wp_p1 = wp + 2'h1;
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assign wp_p2 = wp + 2'h2;
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always @(posedge clk or negedge rst)
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if(!rst) rp <= #1 2'h0;
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else
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if(clr) rp <= #1 2'h0;
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else
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if(re) rp <= #1 rp_p1;
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assign rp_p1 = rp + 2'h1;
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// Fifo Output
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assign dout = mem[ rp ];
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// Fifo Input
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always @(posedge clk)
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if(we) mem[ wp ] <= #1 din;
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// Status
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assign empty = (wp == rp) & !gb;
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assign full = (wp == rp) & gb;
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// Guard Bit ...
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always @(posedge clk)
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if(!rst) gb <= #1 1'b0;
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else
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if(clr) gb <= #1 1'b0;
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else
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if((wp_p1 == rp) & we) gb <= #1 1'b1;
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else
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if(re) gb <= #1 1'b0;
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endmodule
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329
tests/iwls2005/simple_spi/simple_spi_top.v
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329
tests/iwls2005/simple_spi/simple_spi_top.v
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@ -0,0 +1,329 @@
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OpenCores MC68HC11E based SPI interface ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
|
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
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//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: simple_spi_top.v,v 1.5 2004/02/28 15:59:50 rherveille Exp $
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//
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// $Date: 2004/02/28 15:59:50 $
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// $Revision: 1.5 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: simple_spi_top.v,v $
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// Revision 1.5 2004/02/28 15:59:50 rherveille
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// Fixed SCK_O generation bug.
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// This resulted in a major rewrite of the serial interface engine.
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//
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// Revision 1.4 2003/08/01 11:41:54 rherveille
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// Fixed some timing bugs.
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//
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// Revision 1.3 2003/01/09 16:47:59 rherveille
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// Updated clkcnt size and decoding due to new SPR bit assignments.
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//
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// Revision 1.2 2003/01/07 13:29:52 rherveille
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// Changed SPR bits coding.
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//
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// Revision 1.1.1.1 2002/12/22 16:07:15 rherveille
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// Initial release
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//
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//
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//
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// Motorola MC68HC11E based SPI interface
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//
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// Currently only MASTER mode is supported
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module simple_spi_top(
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// 8bit WISHBONE bus slave interface
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input wire clk_i, // clock
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input wire rst_i, // reset (asynchronous active low)
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input wire cyc_i, // cycle
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input wire stb_i, // strobe
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input wire [1:0] adr_i, // address
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input wire we_i, // write enable
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input wire [7:0] dat_i, // data input
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output reg [7:0] dat_o, // data output
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output reg ack_o, // normal bus termination
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output reg inta_o, // interrupt output
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// SPI port
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output reg sck_o, // serial clock output
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output wire mosi_o, // MasterOut SlaveIN
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input wire miso_i // MasterIn SlaveOut
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);
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//
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// Module body
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//
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reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
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wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
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reg [7:0] sper; // Serial Peripheral Extension register
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reg [7:0] treg, rreg; // Transmit/Receive register
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// fifo signals
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wire [7:0] rfdout;
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reg wfre, rfwe;
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wire rfre, rffull, rfempty;
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wire [7:0] wfdout;
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wire wfwe, wffull, wfempty;
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// misc signals
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wire tirq; // transfer interrupt (selected number of transfers done)
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wire wfov; // write fifo overrun (writing while fifo full)
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reg [1:0] state; // statemachine state
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reg [2:0] bcnt;
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//
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// Wishbone interface
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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// dat_i
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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begin
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spcr <= #1 8'h10; // set master bit
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sper <= #1 8'h00;
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end
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else if (wb_wr)
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begin
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if (adr_i == 2'b00)
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spcr <= #1 dat_i | 8'h10; // always set master bit
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if (adr_i == 2'b11)
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sper <= #1 dat_i;
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end
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// write fifo
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assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
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assign wfov = wfwe & wffull;
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// dat_o
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always @(posedge clk_i)
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case(adr_i) // synopsys full_case parallel_case
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2'b00: dat_o <= #1 spcr;
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2'b01: dat_o <= #1 spsr;
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2'b10: dat_o <= #1 rfdout;
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2'b11: dat_o <= #1 sper;
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endcase
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// read fifo
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assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
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// ack_o
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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ack_o <= #1 1'b0;
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else
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ack_o <= #1 wb_acc & !ack_o;
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// decode Serial Peripheral Control Register
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wire spie = spcr[7]; // Interrupt enable bit
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wire spe = spcr[6]; // System Enable bit
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wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
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wire mstr = spcr[4]; // Master Mode Select Bit
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wire cpol = spcr[3]; // Clock Polarity Bit
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wire cpha = spcr[2]; // Clock Phase Bit
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wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
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// decode Serial Peripheral Extension Register
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wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
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wire [1:0] spre = sper[1:0]; // extended clock rate select
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wire [3:0] espr = {spre, spr};
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// generate status register
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wire wr_spsr = wb_wr & (adr_i == 2'b01);
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reg spif;
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always @(posedge clk_i)
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if (~spe)
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spif <= #1 1'b0;
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else
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spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
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reg wcol;
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always @(posedge clk_i)
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if (~spe)
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wcol <= #1 1'b0;
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else
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wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
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assign spsr[7] = spif;
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assign spsr[6] = wcol;
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assign spsr[5:4] = 2'b00;
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assign spsr[3] = wffull;
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assign spsr[2] = wfempty;
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assign spsr[1] = rffull;
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assign spsr[0] = rfempty;
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// generate IRQ output (inta_o)
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always @(posedge clk_i)
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inta_o <= #1 spif & spie;
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//
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// hookup read/write buffer fifo
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fifo4 #(8)
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rfifo(
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.clk ( clk_i ),
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.rst ( rst_i ),
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.clr ( ~spe ),
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.din ( treg ),
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.we ( rfwe ),
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.dout ( rfdout ),
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.re ( rfre ),
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.full ( rffull ),
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.empty ( rfempty )
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),
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wfifo(
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.clk ( clk_i ),
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.rst ( rst_i ),
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.clr ( ~spe ),
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.din ( dat_i ),
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.we ( wfwe ),
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.dout ( wfdout ),
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.re ( wfre ),
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.full ( wffull ),
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.empty ( wfempty )
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||||
);
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|
||||
//
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// generate clk divider
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reg [11:0] clkcnt;
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always @(posedge clk_i)
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if(spe & (|clkcnt & |state))
|
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clkcnt <= #1 clkcnt - 11'h1;
|
||||
else
|
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case (espr) // synopsys full_case parallel_case
|
||||
4'b0000: clkcnt <= #1 12'h0; // 2 -- original M68HC11 coding
|
||||
4'b0001: clkcnt <= #1 12'h1; // 4 -- original M68HC11 coding
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||||
4'b0010: clkcnt <= #1 12'h3; // 16 -- original M68HC11 coding
|
||||
4'b0011: clkcnt <= #1 12'hf; // 32 -- original M68HC11 coding
|
||||
4'b0100: clkcnt <= #1 12'h1f; // 8
|
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4'b0101: clkcnt <= #1 12'h7; // 64
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4'b0110: clkcnt <= #1 12'h3f; // 128
|
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4'b0111: clkcnt <= #1 12'h7f; // 256
|
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4'b1000: clkcnt <= #1 12'hff; // 512
|
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4'b1001: clkcnt <= #1 12'h1ff; // 1024
|
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4'b1010: clkcnt <= #1 12'h3ff; // 2048
|
||||
4'b1011: clkcnt <= #1 12'h7ff; // 4096
|
||||
endcase
|
||||
|
||||
// generate clock enable signal
|
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wire ena = ~|clkcnt;
|
||||
|
||||
// transfer statemachine
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
begin
|
||||
state <= #1 2'b00; // idle
|
||||
bcnt <= #1 3'h0;
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||||
treg <= #1 8'h00;
|
||||
wfre <= #1 1'b0;
|
||||
rfwe <= #1 1'b0;
|
||||
sck_o <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
wfre <= #1 1'b0;
|
||||
rfwe <= #1 1'b0;
|
||||
|
||||
case (state) //synopsys full_case parallel_case
|
||||
2'b00: // idle state
|
||||
begin
|
||||
bcnt <= #1 3'h7; // set transfer counter
|
||||
treg <= #1 wfdout; // load transfer register
|
||||
sck_o <= #1 cpol; // set sck
|
||||
|
||||
if (~wfempty) begin
|
||||
wfre <= #1 1'b1;
|
||||
state <= #1 2'b01;
|
||||
if (cpha) sck_o <= #1 ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b01: // clock-phase2, next data
|
||||
if (ena) begin
|
||||
sck_o <= #1 ~sck_o;
|
||||
state <= #1 2'b11;
|
||||
end
|
||||
|
||||
2'b11: // clock phase1
|
||||
if (ena) begin
|
||||
treg <= #1 {treg[6:0], miso_i};
|
||||
bcnt <= #1 bcnt -3'h1;
|
||||
|
||||
if (~|bcnt) begin
|
||||
state <= #1 2'b00;
|
||||
sck_o <= #1 cpol;
|
||||
rfwe <= #1 1'b1;
|
||||
end else begin
|
||||
state <= #1 2'b01;
|
||||
sck_o <= #1 ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b10: state <= #1 2'b00;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign mosi_o = treg[7];
|
||||
|
||||
|
||||
// count number of transfers (for interrupt generation)
|
||||
reg [1:0] tcnt; // transfer count
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
tcnt <= #1 icnt;
|
||||
else if (rfwe) // rfwe gets asserted when all bits have been transfered
|
||||
if (|tcnt)
|
||||
tcnt <= #1 tcnt - 2'h1;
|
||||
else
|
||||
tcnt <= #1 icnt;
|
||||
|
||||
assign tirq = ~|tcnt & rfwe;
|
||||
|
||||
endmodule
|
||||
|
||||
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