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Clifford Wolf
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361
tests/i2c_bench/i2c_slave_model.v
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361
tests/i2c_bench/i2c_slave_model.v
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant synthesizable I2C Slave model ////
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//// ////
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//// ////
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//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
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//// John Sheahan (jrsheahan@optushome.com.au) ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001,2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
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//
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// $Date: 2006-09-04 09:08:51 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2005/02/28 11:33:48 rherveille
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// Fixed Tsu:sta timing check.
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// Added Thd:sta timing check.
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//
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// Revision 1.5 2003/12/05 11:05:19 rherveille
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// Fixed slave address MSB='1' bug
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//
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// Revision 1.4 2003/09/11 08:25:37 rherveille
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// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
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//
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// Revision 1.3 2002/10/30 18:11:06 rherveille
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// Added timing tests to i2c_model.
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// Updated testbench.
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//
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// Revision 1.2 2002/03/17 10:26:38 rherveille
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// Fixed some race conditions in the i2c-slave model.
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// Added debug information.
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// Added headers.
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//
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`include "timescale.v"
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module i2c_slave_model (scl, sda);
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//
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// parameters
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//
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parameter I2C_ADR = 7'b001_0000;
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//
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// input && outpus
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//
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input scl;
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inout sda;
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//
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// Variable declaration
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//
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wire debug = 1'b1;
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reg [7:0] mem [3:0]; // initiate memory
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reg [7:0] mem_adr; // memory address
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reg [7:0] mem_do; // memory data output
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reg sta, d_sta;
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reg sto, d_sto;
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reg [7:0] sr; // 8bit shift register
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reg rw; // read/write direction
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wire my_adr; // my address called ??
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wire i2c_reset; // i2c-statemachine reset
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reg [2:0] bit_cnt; // 3bit downcounter
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wire acc_done; // 8bits transfered
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reg ld; // load downcounter
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reg sda_o; // sda-drive level
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wire sda_dly; // delayed version of sda
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// statemachine declaration
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parameter idle = 3'b000;
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parameter slave_ack = 3'b001;
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parameter get_mem_adr = 3'b010;
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parameter gma_ack = 3'b011;
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parameter data = 3'b100;
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parameter data_ack = 3'b101;
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reg [2:0] state; // synopsys enum_state
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//
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// module body
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//
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initial
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begin
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sda_o = 1'b1;
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state = idle;
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mem[0] = 0;
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mem[1] = 0;
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mem[2] = 0;
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mem[3] = 0;
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end
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// generate shift register
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always @(posedge scl)
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sr <= #1 {sr[6:0],sda};
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//detect my_address
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assign my_adr = (sr[7:1] == I2C_ADR);
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// FIXME: This should not be a generic assign, but rather
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// qualified on address transfer phase and probably reset by stop
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//generate bit-counter
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always @(posedge scl)
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if(ld)
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bit_cnt <= #1 3'b111;
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else
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bit_cnt <= #1 bit_cnt - 3'h1;
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//generate access done signal
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assign acc_done = !(|bit_cnt);
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// generate delayed version of sda
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// this model assumes a hold time for sda after the falling edge of scl.
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// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
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// with regards to scl. If the data changes coincident with the clock, the
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// acknowledge is missed
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// Fix by Michael Sosnoski
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assign #1 sda_dly = sda;
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//detect start condition
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always @(negedge sda)
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if(scl)
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begin
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sta <= #1 1'b1;
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d_sta <= #1 1'b0;
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sto <= #1 1'b0;
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if(debug)
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$display("DEBUG i2c_slave; start condition detected at %t", $time);
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end
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else
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sta <= #1 1'b0;
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always @(posedge scl)
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d_sta <= #1 sta;
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// detect stop condition
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always @(posedge sda)
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if(scl)
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begin
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sta <= #1 1'b0;
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sto <= #1 1'b1;
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if(debug)
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$display("DEBUG i2c_slave; stop condition detected at %t", $time);
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end
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else
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sto <= #1 1'b0;
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//generate i2c_reset signal
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assign i2c_reset = sta || sto;
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// generate statemachine
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always @(negedge scl or posedge sto)
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if (sto || (sta && !d_sta) )
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begin
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state <= #1 idle; // reset statemachine
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sda_o <= #1 1'b1;
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ld <= #1 1'b1;
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end
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else
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begin
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// initial settings
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sda_o <= #1 1'b1;
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ld <= #1 1'b0;
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case(state) // synopsys full_case parallel_case
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idle: // idle state
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if (acc_done && my_adr)
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begin
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state <= #1 slave_ack;
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rw <= #1 sr[0];
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sda_o <= #1 1'b0; // generate i2c_ack
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#2;
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if(debug && rw)
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$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
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if(debug && !rw)
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$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
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if(rw)
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begin
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mem_do <= #1 mem[mem_adr % 4];
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if(debug)
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begin
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#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
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#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
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end
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end
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end
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slave_ack:
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begin
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if(rw)
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begin
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state <= #1 data;
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sda_o <= #1 mem_do[7];
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end
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else
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state <= #1 get_mem_adr;
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ld <= #1 1'b1;
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end
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get_mem_adr: // wait for memory address
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if(acc_done)
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begin
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state <= #1 gma_ack;
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mem_adr <= #1 sr; // store memory address
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sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
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if(debug)
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#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
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end
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gma_ack:
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begin
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state <= #1 data;
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ld <= #1 1'b1;
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end
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data: // receive or drive data
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begin
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if(rw)
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sda_o <= #1 mem_do[7];
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if(acc_done)
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begin
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state <= #1 data_ack;
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mem_adr <= #2 mem_adr + 8'h1;
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sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
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if(rw)
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begin
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#3 mem_do <= mem[mem_adr % 4];
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if(debug)
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#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
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end
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if(!rw)
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begin
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mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
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if(debug)
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#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
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end
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end
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end
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data_ack:
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begin
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ld <= #1 1'b1;
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if(rw)
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if(sr[0]) // read operation && master send NACK
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begin
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state <= #1 idle;
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sda_o <= #1 1'b1;
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end
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else
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begin
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state <= #1 data;
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sda_o <= #1 mem_do[7];
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end
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else
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begin
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state <= #1 data;
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sda_o <= #1 1'b1;
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end
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end
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endcase
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end
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// read data from memory
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always @(posedge scl)
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if(!acc_done && rw)
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mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
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// generate tri-states
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assign sda = sda_o ? 1'bz : 1'b0;
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//
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// Timing checks
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//
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wire tst_sto = sto;
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wire tst_sta = sta;
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specify
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specparam normal_scl_low = 4700,
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normal_scl_high = 4000,
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normal_tsu_sta = 4700,
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normal_thd_sta = 4000,
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normal_tsu_sto = 4000,
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normal_tbuf = 4700,
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fast_scl_low = 1300,
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fast_scl_high = 600,
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fast_tsu_sta = 1300,
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fast_thd_sta = 600,
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fast_tsu_sto = 600,
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fast_tbuf = 1300;
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$width(negedge scl, normal_scl_low); // scl low time
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$width(posedge scl, normal_scl_high); // scl high time
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$setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
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$setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
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$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
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$setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
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endspecify
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endmodule
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