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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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13
tests/hana/test_simulation_mod_1_xx.v Normal file
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module test(in1, in2, out);
input in1;
input in2;
output out;
wire synth_net_0;
wire synth_net_1;
BUF synth_BUF_0(.in(synth_net_1), .out(out
));
DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
));
endmodule